| Presentation | 2017-11-07 Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch Tetsuaki Fujimoto, Wataru Takahashi, Kazutoshi Wakabayashi, Takashi Imagawa, Hiroyuki Ochi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This report proposes an optimal implementation of FFT circuit for mixed grained reconfigurable architecture using via-switch. In the target architecture, the programmable routing resources are implemented in the metal layers thanks to via-switch, and as a result, rich amount of functional resources can be implemented in the substrate layer. To make full use of the rich arithmetic resources, the proposed method realizes a high-speed one-cycle-per-stage fully-parallelized processing by using $N/2$ butterfly units for $N$-point FFT. It also introduces fixed-stride-type FFT that makes the data access pattern of all stages fixed, to reduce multiplexers drastically. Compared with the Cooley-Tukey FFT, the required nets for the 64-point FFT are reduced by about 26%. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | fast Fourier transform / butterfly operation / fixed-stride-type FFT / parallelization |
| Paper # | VLD2017-38,DC2017-44 |
| Date of Issue | 2017-10-30 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2017/11/6(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kumamoto-Kenminkouryukan Parea |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2017 -New Field of VLSI Design- |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Michiko Inoue(NAIST) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Kiyoharu Hamaguchi(Shimane Univ.) / 渡辺 晴美(東海大) / Masahiro Goshima(NII) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Kazuya Kodama(NII) / Hideaki Kimata(NTT) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / Satoshi Fukumoto(NTT) / Hidetsugu Irie(Kyoto Sangyo Univ.) / Takashi Miyoshi(Tokyo Inst. of Tech.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Kazuya Kodama(Nihon Univ.) / Hideaki Kimata(Toyohashi Univ. of Tech.) / (Univ. of Tokyo) / (Panasonic) / (Nagoya Univ.) |
| Assistant | / Masayuki Arai(Nihon Univ.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yuichi Akage(NTT) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasutaka Matsuo(NHK) / Kazuya Hayase(NTT) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch |
| Sub Title (in English) | |
| Keyword(1) | fast Fourier transform |
| Keyword(2) | butterfly operation |
| Keyword(3) | fixed-stride-type FFT |
| Keyword(4) | parallelization |
| 1st Author's Name | Tetsuaki Fujimoto |
| 1st Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| 2nd Author's Name | Wataru Takahashi |
| 2nd Author's Affiliation | NEC Corporation(NEC) |
| 3rd Author's Name | Kazutoshi Wakabayashi |
| 3rd Author's Affiliation | NEC Corporation(NEC) |
| 4th Author's Name | Takashi Imagawa |
| 4th Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| 5th Author's Name | Hiroyuki Ochi |
| 5th Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| Date | 2017-11-07 |
| Paper # | VLD2017-38,DC2017-44 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-273,DC-274 |
| Page | pp.pp.67-72(VLD), pp.67-72(DC), |
| #Pages | 6 |
| Date of Issue | 2017-10-30 (VLD, DC) |