Presentation | 2017-11-07 On low power oriented test pattern compaction using SAT solver Yusuke Matsunaga, |
---|---|
PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper proposes a test pattern compaction method under power consumption constraint, which uses SAT solver based random sampling. First, candidate patterns are generated using XOR constraint based SAT model sampling, which adds randomly generated constraints to the original problem, then test pattern set is derived by solving minimum set covering problem. Experiments show that increasing the number of candidate patterns directly leads better solution, which means the proposed heuristic is very effective and robust. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | test pattern generation / signal transition activity / SAT / random sampling |
Paper # | VLD2017-43,DC2017-49 |
Date of Issue | 2017-10-30 (VLD, DC) |
Conference Information | |
Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
---|---|
Conference Date | 2017/11/6(3days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Kumamoto-Kenminkouryukan Parea |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Design Gaia 2017 -New Field of VLSI Design- |
Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Michiko Inoue(NAIST) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Kiyoharu Hamaguchi(Shimane Univ.) / 渡辺 晴美(東海大) / Masahiro Goshima(NII) |
Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Kazuya Kodama(NII) / Hideaki Kimata(NTT) |
Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / Satoshi Fukumoto(NTT) / Hidetsugu Irie(Kyoto Sangyo Univ.) / Takashi Miyoshi(Tokyo Inst. of Tech.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Kazuya Kodama(Nihon Univ.) / Hideaki Kimata(Toyohashi Univ. of Tech.) / (Univ. of Tokyo) / (Panasonic) / (Nagoya Univ.) |
Assistant | / Masayuki Arai(Nihon Univ.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yuichi Akage(NTT) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasutaka Matsuo(NHK) / Kazuya Hayase(NTT) |
Paper Information | |
Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
---|---|
Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | On low power oriented test pattern compaction using SAT solver |
Sub Title (in English) | |
Keyword(1) | test pattern generation |
Keyword(2) | signal transition activity |
Keyword(3) | SAT |
Keyword(4) | random sampling |
1st Author's Name | Yusuke Matsunaga |
1st Author's Affiliation | Kyushu University(Kyushu Univ.) |
Date | 2017-11-07 |
Paper # | VLD2017-43,DC2017-49 |
Volume (vol) | vol.117 |
Number (no) | VLD-273,DC-274 |
Page | pp.pp.95-99(VLD), pp.95-99(DC), |
#Pages | 5 |
Date of Issue | 2017-10-30 (VLD, DC) |