Information and Systems-Dependable Computing(Date:2003/11/21)

Presentation
Design of Hierarchical Multi-processor architecture for Automatic Generation

Daisuke OKAWA,  Hideto NISHIKADO,  Takehiro HARA,  Toshiyuki KATO,  Hironori YAMAUCHI,  

[Date]2003/11/21
[Paper #]DC2003-52
A Hardware/Software Cosynthesis Method for CAM Processor with Area Constraints

Yuichiro ISHIKAWA,  Yuichiro MIYAOKA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2003/11/21
[Paper #]DC2003-53
A Improvement Method of a Processor for a Embedded System on an FPGA

Hideo ARAKI,  Toshiro KUTSUWA,  Katsumi HARASHIMA,  

[Date]2003/11/21
[Paper #]DC2003-54
Reducing Memory Access Stage of Pipelined CISC Processor by Self-Hazard

Takahiro Watanabe,  Noriko Miyazaki,  Kazuhito Ito,  

[Date]2003/11/21
[Paper #]DC2003-55
Dedicated Circuit for Accelerating Permutation on Microprocessor

Kazuya KIMURA,  Takehiro OHASHI,  Naofumi TAKAGI,  Kazuyoshi TAKAGI,  

[Date]2003/11/21
[Paper #]DC2003-56
Modeling and Simulation of Bus System with Hierarchical Bus Arbitration Policy in Java

Tomo KITAGUCHI,  Tadaaki TANIMOTO,  Akio NAKATA,  Teruo HIGASHINO,  

[Date]2003/11/21
[Paper #]DC2003-57
Quantum Search Hardware Simulator based on Decomposition of the State Space

Ayahiro TAKAKI,  Masaki NAKANISHI,  Shigeru YAMASHITA,  Katsumasa WATANABE,  

[Date]2003/11/21
[Paper #]DC2003-58
Architecture for active software that can rearrange active functions

Mitsuru TOMONO,  Masaki NAKANISHI,  Shigeru YAMASHITA,  Katsumasa WATANAGE,  

[Date]2003/11/21
[Paper #]DC2003-59
Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells

Tetsuya IIZUKA,  Makoto IKEDA,  Kunihiro ASADA,  

[Date]2003/11/21
[Paper #]DC2003-60
低温域におけるMoveの制限によるSimulated Annealing法を用いたパッキングの高速化(VLSIの設計/検証/テスト及び一般 配置配線)(デザインガイア2003 -VLSI設計の新しい大地を考える研究会-)

Seiji UCHIDA,  Atsushi TAKAHASHI,  

[Date]2003/11/21
[Paper #]DC2003-61
A Hierarchical Standard-Cell Placement Method Based on Wire Length-Driven Clustering

Hajime KUBOTA,  Shin'ichi WAKABAYASHI,  Tetsushi KOIDE,  Toshio TSUJI,  

[Date]2003/11/21
[Paper #]DC2003-62
A Fast Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effect

Keiji KIDA,  Xiaoke ZHU,  Changwen ZHUANG,  Yashuhiro TAKASHIMA,  Shigetoshi NAKATAKE,  

[Date]2003/11/21
[Paper #]DC2003-63
Detail Routing Restriction for Crosstalk Delay Prevention

Tomoyuki YODA,  Mikio NAKANO,  Fumihiro MINAMI,  Masaaki YAMADA,  

[Date]2003/11/21
[Paper #]DC2003-64
Equi-Distance Routing for Plural Nets on Slant Grid

Yukiko KUBO,  Hiroshi MIYASHITA,  Yoji KAJITANI,  Kazuyuki TATEISHI,  

[Date]2003/11/21
[Paper #]DC2003-65
Multi-Level Placement with Circuit Schema Based Clustering in Analog IC Layouts

Takashi NOJIMA,  Xiaoke ZHU,  Yasuhiro TAKASHIMA,  Shigetoshi NAKATAKE,  Yoji KAJITANI,  

[Date]2003/11/21
[Paper #]DC2003-66
A Fast Algorithm for Rectilinear Block Packing Using SSP

Akira IKEDA,  Chikaaki KODAMA,  Akihiro NAKAGOMI,  Kunihiro FUJIYOSHI,  

[Date]2003/11/21
[Paper #]DC2003-67
Ensuring Signal Integrity on GHz Signals Using the Segmental Transmission Line

Moritoshi YASUNAGA,  Ikuo YOSHIHARA,  

[Date]2003/11/21
[Paper #]DC2003-68
Analysis of Ground Noise in Large-scale Digital Circuits

Tomohiko SUGIMOTO,  Takeshi OKUMOTO,  Makoto NAGATA,  Kazuo TAKI,  

[Date]2003/11/21
[Paper #]DC2003-69
Power Supply Noise Reduction using Stubs

Toru NAKURA,  Makoto IKEDA,  Kunihiro ASADA,  

[Date]2003/11/21
[Paper #]DC2003-70
Minimization of Average Path Lengths for Heterogeneous MDDs

Shinobu NAGAYAMA,  Tsutomu SASAO,  

[Date]2003/11/21
[Paper #]DC2003-71
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