| Presentation | 2003/11/21 Design of Hierarchical Multi-processor architecture for Automatic Generation Daisuke OKAWA, Hideto NISHIKADO, Takehiro HARA, Toshiyuki KATO, Hironori YAMAUCHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We proposed a multi-processor system based software and hardware co-design platform intended for generating real-time applications. In this system, we adopt the distributed memory type multi-processor architecture with hierarchical network which can respond to the various scale of multi-processor fiexibly. In a distributed memory type multi-processor, since the overhead by communication between PEs (Processor Element) influences the processing performance of multi-processor system, performing communication between PEs efficiently is called for. We have examined and designed a PE architecture and PE network SW, and we have experimented performance comparison by simulation with FFT program. So we are reporting here. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Multi-processor system / Hardware-Software Co-design / System on Chip |
| Paper # | DC2003-52 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2003/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Hierarchical Multi-processor architecture for Automatic Generation |
| Sub Title (in English) | |
| Keyword(1) | Multi-processor system |
| Keyword(2) | Hardware-Software Co-design |
| Keyword(3) | System on Chip |
| 1st Author's Name | Daisuke OKAWA |
| 1st Author's Affiliation | VLSI center, Ritsumeikan University() |
| 2nd Author's Name | Hideto NISHIKADO |
| 2nd Author's Affiliation | VLSI center, Ritsumeikan University |
| 3rd Author's Name | Takehiro HARA |
| 3rd Author's Affiliation | VLSI center, Ritsumeikan University |
| 4th Author's Name | Toshiyuki KATO |
| 4th Author's Affiliation | VLSI center, Ritsumeikan University |
| 5th Author's Name | Hironori YAMAUCHI |
| 5th Author's Affiliation | VLSI center, Ritsumeikan University |
| Date | 2003/11/21 |
| Paper # | DC2003-52 |
| Volume (vol) | vol.103 |
| Number (no) | 480 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |