Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2013] | [2014] | [2015] | [2016] | [2017] | [2018] | [2019] | [Japanese] / [English]
RECONF2016-40
Design for 3-Demensional Sound Processor using a High-Level Synthesis
Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.)
pp. 1 - 6
RECONF2016-41
Variable Pipeline Ultra Low-power Coarse Grained Reconfigurable Accelelator
Naoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano (Keio Univ.)
pp. 7 - 12
RECONF2016-42
A Novel Merge Network for FPGA Sorting Accelerators
Makoto Saitoh, Susumu Mashimo, Thiem Van Chu, Kenji Kise (Tokyotech)
pp. 13 - 18
RECONF2016-43
Hardware implementation of PLC Instructions by high level synthesis
Ishigaki Yoshiki, Tanaka Tasuku, Fujieda Naoki, Ichikawa Shuichi (TUT)
pp. 19 - 24
RECONF2016-44
(See Japanese page.)
pp. 25 - 28
RECONF2016-45
Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm
Toshiki Higashi, Hiroyuki Ochi (Ritsumeikan Univ.)
pp. 29 - 34
RECONF2016-46
Development of power estimation tool for three dimensional FPGA
Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 35 - 40
RECONF2016-47
Preliminary experimental platform for FlexPower FPGA evaluation
Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike (AIST)
pp. 41 - 46
RECONF2016-48
[Invited Talk]
FPGA Development using HLS for Software Engineers
Kenichiro Mitsuda, Hiroshi Owada, Shinji Yamamoto (ISP)
p. 47
RECONF2016-49
[Keynote Address]
CMOS Annealing Machine to Solve Combinatorial Optimization Problems for IoT Era
Masanao Yamaoka (Hitachi)
pp. 49 - 54
RECONF2016-50
[Keynote Address]
The development of video coding technology and contribution to HD transition
Akira Nakagawa (Fujitsu Labs.)
p. 55
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.