Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2015-77
Circuit Design of Reconfigurable Logic and Comparison of the Methods
Junki Kato, Shigeyoshi Watanabe, Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura (SIT)
pp. 1 - 6
VLD2015-78
FPGA routing structure based on H-Tree topology
Yuki ishii, Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 7 - 12
VLD2015-79
Pipelining in Coarse Grained Reconfigurable Accelerator CMA
Naoki Ando, Koichiro Masuyama, Yu Fujita, Hideharu Amano (Keio Univ.)
pp. 13 - 18
VLD2015-80
A Low-Latency Batch Processing for Stream Data Using FPGA NIC
Kohei Nakamura, Ami Hayashi, Hiroki Matsutani (Keio Univ.)
pp. 19 - 24
VLD2015-81
Performance Evaluations on Reduction and Transformation of Spark Using GPU
Yasuhiro Ohno, Shin Morishima, Hiroki Matsutani (Keio Univ.)
pp. 25 - 30
VLD2015-82
GPGPU Parallelization of a cerebral cortex model BESOM
Hidemoto Nakada, Tatsuhiko Inoue, Yuji Ichisugi (AIST)
pp. 31 - 36
VLD2015-83
GPGPU Implementation of the MSD Method for Outlier Detection and Its Experimental Evaluation
Shotaro Asano, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.)
pp. 37 - 42
VLD2015-84
Cost Estimation Method based on CPU Architecture for Relational Database Query Optimization
Tsuyoshi Tanaka (Tokyo Metropolitan Univ./Hitachi), Hiroshi Ishikawa (Tokyo Metropolitan Univ.)
pp. 67 - 72
VLD2015-85
Performance Improvement on In-Kernel NOSQL Cache for Range Queries
Korechika Tamura, Hiroki Matsutani (Keio Univ.)
pp. 73 - 78
VLD2015-86
FPGA-based Parallel Processing of Sliding-Window Aggregate Queries on Data Streams
Yoshimitsu Ogawa, Yasin Oge, Masato Yoshimi, Celimuge Wu, Tsutomu Yoshinaga (UEC)
pp. 79 - 84
VLD2015-87
A Chip Evaluation of the Heat Generation in 3D stacked LSI
Tatsuya Wada, Kimiyosi Usami (Shibaura IT)
pp. 85 - 90
VLD2015-88
Implementation and evaluation of Dynamic Multi-Vth methodology in Silicon-on-Thin-BOX
Shohei Io, Hanano Suzuki, Shohei Nakamura, Kimiyoshi Usami (Shibaura IT)
pp. 91 - 96
VLD2015-89
Control Signal Extraction for Backward Sequential Clock Gating
Tomoya Goto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.)
pp. 97 - 102
VLD2015-90
[Fellow Memorial Lecture]
Failure May teach Success
-- In Computer Architecture Research based on Real hardware --
Hideharu Aamano (Keio Univ.)
pp. 121 - 124
VLD2015-91
Design of Stencil Computation based on Building-Cube Method on an FPGA Accelerator with High Level Synthesis
Rie Soejima, Koji Okina, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 125 - 130
VLD2015-92
FPGA-based Tsunami Simulator developed by using stream-computing hardware compiler
Kohei Nagasu, Kentaro Sano (Tohoku Univ.), Fumiya Kono, Naohito Nakasato (The Univ. of Aizu)
pp. 131 - 136
VLD2015-93
A Parallel Algorithm for Realizing the MacCormack Scheme in Computational Fluid Dynamics and its FPGA Implementation
Yusuke Haga, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.)
pp. 137 - 142
VLD2015-94
Topological Analysis of Low-Powered 3D-TESH Network
Faiz Al Faisal (JAIST), Hafizur Rahman (IIUM), Yasushi Inoguchi (JAIST)
pp. 143 - 148
VLD2015-95
An Efficient NoC with Decentralized Routers
Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Tadao Nakamura (Keio Univ.)
pp. 149 - 154
VLD2015-96
A performance evaluation of PEACH3
Takahiro Kaneda, Chiharu Tsuruta (Keio Univ), Toshihiro Hanawa (UTokyo), Hideharu Amano (Keio Univ)
pp. 155 - 160
VLD2015-97
Latency Reduction on Inter-Component Communication across Racks using FSO
Hiroaki Hara, Tomoya Ozaki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.)
pp. 161 - 166
VLD2015-98
Performance Improvement on Music Fingerprint Searching from Large-Scale Database by Using Probabilistic Bias
Masahiro Fukuda, Yasushi Inoguchi (JAIST)
pp. 167 - 172
VLD2015-99
Discussion on FPGA implementation of real-time human detection using FIND features
Yoshiki Hayashida, Masahito Oishi, Ryo Fujita, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 173 - 178
VLD2015-100
FPGA Implementation of a Peak Detection System using AMPD Algorithm
Fumihiko Iwasaki, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ)
pp. 179 - 184
VLD2015-101
Power Optimization of a Reconfigurable Accelerator by Middle-grained Body Bias Control
Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Hideharu Amano (Keio Univ.)
pp. 185 - 190
VLD2015-102
Power Reduction of TLB using Body Bias Control on SOTB
Daiki Kawase, Hayate Okuhara, Hideharu Amano (Keio Univ.)
pp. 191 - 196
VLD2015-103
An Architectural Optimization for Software Defined SSD using Full System Simulator
Shun Gokita, Satoshi Kazama, Seiki Shibata, Shinya Kuwamura, Eiji Yoshida, Junji Ogawa (FLL)
pp. 197 - 202
VLD2015-104
Mainframe Assembly to C translation in Legacy Migration
Daisuke Fujiwara, Nagisa Ishiura, Ryo Sakai (Kwansei Gakuin Univ.), Ryo Aoki, Takashi Ogawara (SYSTEM'S)
pp. 203 - 208
VLD2015-105
A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations
Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 209 - 214
VLD2015-106
Binary Synthesis Implementing External Interrupt Handler as Independent Module
Naoya Ito, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM)
pp. 215 - 220
VLD2015-107
Write-Reduction using Encoding data on MLC for Non-Volatile Memories
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 221 - 225
VLD2015-108
A Realization of Deep Convolutional Neural Network using the Nested RNS on an FPGA including the Constant Division
Hiroki Nakahara (Ehime Univ.), Tsutomu Sasao (Meiji Univ.), Hisashi Iwamoto (REVSONIC Corp.)
pp. 227 - 232
VLD2015-109
Implementation of TRAX Solver with Mate Structure
Yasuhiro Takashima, Takaaki Yahata, Saki Yamaguchi, Komei Nomura (Univ. of Kitakyushu)
pp. 233 - 236
VLD2015-110
Search of Evaluation Function with Genetic Algorithm and UML Model-based Development for TRAX Player
Ryo Tamaki, Naohiko Shimizu (Tokai Univ.)
pp. 237 - 242
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.