Print edition: ISSN 0913-5685
Online edition: ISSN 2432-6380
[TOP] | [2006] | [2007] | [2008] | [2009] | [2010] | [2011] | [2012] | [Japanese] / [English]
RECONF2005-53
Variable Grain Logic Cell Architecture for Reconfigurable Device
Motoki Amagasaki, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 1 - 6
RECONF2005-54
Implementation of Basic Function Blocks for Variable Grain Logic Cell
Naoto Hamabe, Hideaki Nakayama, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 7 - 12
RECONF2005-55
A study of reconfigurable hardware architecture for physical layer of wireless access systems
Yoshio Wada (Samsung Yokohama Research Institute)
pp. 13 - 18
RECONF2005-56
Implementation of 1-D/2-D FFT on the Dynamically Reconfigurable Processor DAPDNA-2
Kosuke Shiba, Atsushi Imaizumi, Takeshi Sakuma (IPFlex)
pp. 19 - 24
RECONF2005-57
Adaptive Computling on the Dynamically Reconfigurable Processor DRP-1
Shohei Abe, Yohei Hasegawa (Keio Univ.), Takao Toi, Takeshi Inuo (NEC System Devices Research Labs.), Hideharu Amano (Keio Univ.)
pp. 25 - 30
RECONF2005-58
A New Design Method for Implementing Real-Time Embedded Systems on Dynamically Reconfigurable Processors
Ryo Nakahashi, Tomoya Kitani (Osaka Univ.), Keiichi Yasumoto (NAIST), Akio Nakata, Teruo Higashino (Osaka Univ.)
pp. 31 - 36