Today, low jitter clock synthesizers are one of the most demanding components in various systems. Devices sustained by energy harvesters or low-capacity battery must support low-voltage and low-power operation. This puts a challenge on clock synthesizer designs considering the frequency tuning range, phase noise and power consumption. As one of the types of clock synthesizer, phase-locked loop (PLL) based clock multipliers are commonly implemented in modern systems-on-chip, that multiply a low-frequency reference provided by a crystal oscillator. As noted, commonly implemented type-II PLLs using low reference frequencies cannot provide sufficient voltage-controlled oscillator noise suppression bandwidth. In contrast to PLLs, injection-locked clock multipliers (ILCMs) lock oscillation frequency to an integer multiplier reference clock by injection pulses. In which, the noise performance of the VCO, including the flicker noise, has a significant influence on the ILCM’s phase noise performance. As CMOS scales, the MOS transistor flicker noise will further degrade the close-in PN, thus limiting the achievable jitter performance of the PLL or ILCM and the data rate of the transceiver. It is worth noting that conventional designs operate with larger than 0.3mW power consumption. Since the Figure-of-Merit (FoM) is a function of the power dissipation and the achievable phase noise performance, VCO with ultralow power consumption and good phase noise performance can also achieve good FoM and be attractive for low power applications such as digital PLL and BLE transceivers. Also, the open loop operation of VCO can be helpful in saving TX power which requires VCO to have both low 1/f3 and 1/f2 phase noise. In this paper, a sub-100 μW VCO based on a single transformer structure is proposed with low flicker noise corner and ultra-low power consumption. The analysis of the transformer-based tank impedance, startup condition, and flicker noise is detailed in this work and verified with more detailed simulation/measurement results. Compared with the current state-of-the-art, the VCO in this work achieves much lower power consumption with an excellent flicker noise performance. To verify the high performances of the VCO, a low-power ILCM is built based on this ULP VCO targeting for high jitter performance (e.g., ＜100 fs) with a sub-300 μW power consumption, which is difficult to realize with the conventional structure. Finally, this proposed ILCM demonstrates its applicability in high jitter performance and low-power clock generator applications.