| Presentation | 2009-06-05 Study for extracting the characteristics of LSI power supply at high frequency including the parasitic coupling between package and chip Tomohiro KITA, Yuichi MABUCHI, Hiroshi TANAKA, Takashi HISAKADO, Osami WADA, Atsushi NAKAMURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | To establish more efficient EMC designing method of electronic apparatuses, constructing a precise EMC macromodel of IC/LSI power supply blocks is needed for simulation of noise levels of current flowing through the power distribution networks. For modeling in GHz frequency range, the characteristics between a chip and its package, or a package and a PCB should be considered. In this report, the impedance characteristics of a chip mounted on a BGA package is evaluated based on bare-chip characteristics extracted by measurement, package parameters identified by numerical simulation, and the estimated value of capacitance existing between the silicon die and the package plane. Good agreement between simulation and measurement is obtained up to about 4GHz. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | LSI package / EMC macromodel / chip-package co-design / parasitic capacitance / LSI power distribution network |
| Paper # | EMCJ2009-31 |
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| Conference Information | |
| Committee | EMCJ |
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| Conference Date | 2009/5/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Electromagnetic Compatibility (EMCJ) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Study for extracting the characteristics of LSI power supply at high frequency including the parasitic coupling between package and chip |
| Sub Title (in English) | |
| Keyword(1) | LSI package |
| Keyword(2) | EMC macromodel |
| Keyword(3) | chip-package co-design |
| Keyword(4) | parasitic capacitance |
| Keyword(5) | LSI power distribution network |
| 1st Author's Name | Tomohiro KITA |
| 1st Author's Affiliation | Department of Electrical Engineering, Kyoto University() |
| 2nd Author's Name | Yuichi MABUCHI |
| 2nd Author's Affiliation | Department of Electrical Engineering, Kyoto University |
| 3rd Author's Name | Hiroshi TANAKA |
| 3rd Author's Affiliation | Department of Electrical Engineering, Kyoto University |
| 4th Author's Name | Takashi HISAKADO |
| 4th Author's Affiliation | Department of Electrical Engineering, Kyoto University |
| 5th Author's Name | Osami WADA |
| 5th Author's Affiliation | Department of Electrical Engineering, Kyoto University |
| 6th Author's Name | Atsushi NAKAMURA |
| 6th Author's Affiliation | Renesas Technology Corporation |
| Date | 2009-06-05 |
| Paper # | EMCJ2009-31 |
| Volume (vol) | vol.109 |
| Number (no) | 76 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |