Presentation | 2007-01-30 A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation Tsuyoshi IWAGAKI, Satoshi OHTAKE, Mineo KANEKO, Hideo FUJIWARA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper discusses a test generation framework using checker circuits. In this framework, some properties, which should be considered during test generation, are expressed as a checker circuit, then; for the circuit under test attached to the checker circuit and its mask circuit, test generation is performed by using existing techniques. Any test set generated under the framework satisfies all the properties given by the user. This framework can handle various properties together by using checker circuits, and it can easily be implemented. In this paper, as a possible application of the framework, path delay test generation through stuck-at test generation is presented. Experimental results show that the proposed framework is feasible and effective. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | test generation framework / checker circuit / mask circuit / path delay test generation / stuck-at test generation / false path identification |
Paper # | CAS2006-76 |
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Conference Information | |
Committee | CAS |
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Conference Date | 2007/1/23(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Circuits and Systems (CAS) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation |
Sub Title (in English) | |
Keyword(1) | test generation framework |
Keyword(2) | checker circuit |
Keyword(3) | mask circuit |
Keyword(4) | path delay test generation |
Keyword(5) | stuck-at test generation |
Keyword(6) | false path identification |
1st Author's Name | Tsuyoshi IWAGAKI |
1st Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology() |
2nd Author's Name | Satoshi OHTAKE |
2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
3rd Author's Name | Mineo KANEKO |
3rd Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology |
4th Author's Name | Hideo FUJIWARA |
4th Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
Date | 2007-01-30 |
Paper # | CAS2006-76 |
Volume (vol) | vol.106 |
Number (no) | 512 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |