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Presentation
2007-01-30 12:20
A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation
Tsuyoshi Iwagaki
(
JAIST
),
Satoshi Ohtake
(
NAIST
),
Mineo Kaneko
(
JAIST
),
Hideo Fujiwara
(
NAIST
)
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