| Presentation | 2017-02-24 A New Computing A New Computing Architecture Using Ising Spin Model Implemented on FPGA for Solving Combinatorial Optimization ProblemsArchitecture by Ising Spin Model for Solving Combinatorial Optimization Problems Implemented on FPGA Yusuke Kihara, Mitsuki Ito, Takanari Saito, Masayuki Shiomura, Shotaro Sakai, Jun-ichi Shirakashi, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, the new computing architecture using Ising spin model has been attracting considerable attention. It is well known that Ising spin model represents the physical properties of ferromagnetic materials in terms of statistical mechanics. In this model, the spin states are varied in order to minimize the system energy automatically, by the interaction between connected adjacent spins. The new computing maps combinatorial optimization problems on Ising model to express the behavior of magnetic spins and solves these problems by ground state search operations exploiting its convergence property. In this report, the new computing architecture using Ising spin model was implemented using FPGA (Field Programmable Gate Array), and the Ising computing based on FPGA was investigated to solve combinatorial optimization problems. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Ising Spin Model / Combinatorial Optimization Problems / Field Programmable Gate Array |
| Paper # | ED2016-134,SDM2016-151 |
| Date of Issue | 2017-02-17 (ED, SDM) |
| Conference Information | |
| Committee | ED / SDM |
|---|---|
| Conference Date | 2017/2/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Centennial Hall, Hokkaido Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Functional nanodevices and related technologies |
| Chair | Koichi Maezawa(Univ. of Toyama) / Tatsuya Kunikiyo(Renesas) |
| Vice Chair | Kunio Tsuda(Toshiba) / Takahiro Shinada(Tohoku Univ.) |
| Secretary | Kunio Tsuda(JAIST) / Takahiro Shinada(New JRC) |
| Assistant | Masataka Higashiwaki(NICT) / Toshiyuki Oishi(Saga Univ.) / Hiroya Ikeda(Shizuoka Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Electron Devices / Technical Committee on Silicon Device and Materials |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A New Computing A New Computing Architecture Using Ising Spin Model Implemented on FPGA for Solving Combinatorial Optimization ProblemsArchitecture by Ising Spin Model for Solving Combinatorial Optimization Problems Implemented on FPGA |
| Sub Title (in English) | |
| Keyword(1) | Ising Spin Model |
| Keyword(2) | Combinatorial Optimization Problems |
| Keyword(3) | Field Programmable Gate Array |
| 1st Author's Name | Yusuke Kihara |
| 1st Author's Affiliation | Tokyo University of Agriculture and Technology(Tokyo Univ. of Agr. & Tech.) |
| 2nd Author's Name | Mitsuki Ito |
| 2nd Author's Affiliation | Tokyo University of Agriculture and Technology(Tokyo Univ. of Agr. & Tech.) |
| 3rd Author's Name | Takanari Saito |
| 3rd Author's Affiliation | Tokyo University of Agriculture and Technology(Tokyo Univ. of Agr. & Tech.) |
| 4th Author's Name | Masayuki Shiomura |
| 4th Author's Affiliation | Tokyo University of Agriculture and Technology(Tokyo Univ. of Agr. & Tech.) |
| 5th Author's Name | Shotaro Sakai |
| 5th Author's Affiliation | Tokyo University of Agriculture and Technology(Tokyo Univ. of Agr. & Tech.) |
| 6th Author's Name | Jun-ichi Shirakashi |
| 6th Author's Affiliation | Tokyo University of Agriculture and Technology(Tokyo Univ. of Agr. & Tech.) |
| Date | 2017-02-24 |
| Paper # | ED2016-134,SDM2016-151 |
| Volume (vol) | vol.116 |
| Number (no) | ED-471,SDM-472 |
| Page | pp.pp.23-28(ED), pp.23-28(SDM), |
| #Pages | 6 |
| Date of Issue | 2017-02-17 (ED, SDM) |