Information and Systems-Speech(Date:2002/06/21)

Presentation
表紙

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[Date]2002/6/21
[Paper #]
目次

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[Date]2002/6/21
[Paper #]
Consideration of Noise Subtraction Coefficient in Noise Reduction System Based on Modified DFT Pair

Isao NAKANISHI,  Yoshimitsu TORIGOE,  Yoshio ITOH,  Yutaka FUKUI,  

[Date]2002/6/21
[Paper #]DSP2002-66
DOA Estimation of Multiple Sound Sources by Using Parameter Estimation Technique

Ryuji KATSURA,  Yongmei LI,  Kazunori SUGAHARA,  Ryosuke KONISHI,  

[Date]2002/6/21
[Paper #]DSP2002-67
A VLSI implementation of a word recognition system for low-power design

Shingo Yoshizawa,  Yoshikazu Miyanaga,  Norinobu Yoshida,  Naoya Wada,  

[Date]2002/6/21
[Paper #]DSP2002-68
Architecture of Pseudo Random Noise Code Generator for Next-Generation GNSS Receiver

Tsutomu OKADA,  Tsubasa UCHIDA,  Takao ONOYE,  Isao SHIRAKAWA,  

[Date]2002/6/21
[Paper #]DSP2002-69
Multi-Tone Curve Fitting Algorithms for ADC Testing

YOSHITO MOTOKI,  Hidetake SUGAWARA,  Haruo KOBAYASHI,  Takanori KOMURO,  Hiroshi SAKAYORI,  

[Date]2002/6/21
[Paper #]DSP2002-70
A Consideration on the Structure of DC-DC Converters

Tetsuo NISHI,  Takashi OGISHIMA,  Masato OGATA,  

[Date]2002/6/21
[Paper #]DSP2002-71
Design of a Compact PLL with New Active Loop Filter Circuit

Shiro Dosho,  

[Date]2002/6/21
[Paper #]DSP2002-72
Invertible Deinterlacing with Variable Coefficients

Shogo MURAMATSU,  Takuma ISHIDA,  Hisakazu KIKUCHI,  Tetsuro KUGE,  

[Date]2002/6/21
[Paper #]DSP2002-73
Gray-Scale/Color Image-Segmentation Architecture based on Cell-Network

Takashi MORIMOTO,  Youmei HARADA,  Tetsushi KOIDE,  Hans Jurgen MATTAUSCH,  

[Date]2002/6/21
[Paper #]DSP2002-74
Parallel Octave for Cluster Computers

Hayato FUJIWARA,  Takafumi AOKI,  Tatsuo HIGUCHI,  

[Date]2002/6/21
[Paper #]DSP2002-75
Development of the high-performance microcomputer "M32R" by prototyping method with FPGA

Masami NAKAJIMA,  Hiroyuki KONDO,  Hirokazu TAKATA,  Mamoru SAKUGAWA,  Takashi HIGUCHI,  Sugako OHTANI,  Hitoshi YAMAMOTO,  Tomoyoshi INASAKA,  Kenji SHIRAI,  Toru SHIMIZU,  

[Date]2002/6/21
[Paper #]DSP2002-76
An Integrated System Mimicking Brain Functions for Image Recognision

Takashi MORIE,  Atsushi IWATA,  

[Date]2002/6/21
[Paper #]DSP2002-77
A Parallelizing Compile Algorithm in Hardware/Software Cosynthesis System for Processor Cores with Packed SIMD Type Instruction Sets

Nobuharu SUZUKI,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2002/6/21
[Paper #]DSP2002-78
A Hardware/Software Partitioning Algorhithm for Image Processors with a Packed SIMD Type Instruction Set

Koichi TACHIKAKE,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2002/6/21
[Paper #]DSP2002-79
The Layout Architecture of Flexible Cells with Continuously Variable Drive Capabilities and Its Application to Static CMOS Combinatorial Logic Circuits

Takanori Yoshiyama,  Toshiro Akino,  

[Date]2002/6/21
[Paper #]DSP2002-80
The Layout Architecture of Flexible Cells with Continuously Variable Drive Capabilities and Its Application to Dynamic CMOS Combinatorial Logic Circuits

Makoto Nagata,  Toshiro Akino,  

[Date]2002/6/21
[Paper #]DSP2002-81
[OTHERS]

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[Date]2002/6/21
[Paper #]