IEICE Technical Committee

Information and Systems-Image Engineering(Date:2023/03/01)

Presentation

Circuit Optimization and Simulation Evaluation for Ultra-Low Voltage of LRPUF Using Manufacturing Variability of Leakage Current

Shunkichi Hata(SIT), Kimiyoshi Usami(SIT),

[Date]2023-03-01
[Paper #]VLD2022-77,HWS2022-48

Measured Evaluation of BTI Degradation in a 65nm FDSOI Process using Ring Oscillators with Same Circuit Structure

Daisuke Kikuta(KIT), Ryo Kishida(TPU), Kazutoshi Kobayashi(KIT),

[Date]2023-03-01
[Paper #]VLD2022-73,HWS2022-44

Large-scale SAT Solution Search by FPGA Implementation of Attraction-Repulsion Control-Type Amoeba Algorithm

Torao Okuyama(Keio Univ.), Masashi Aono(Amoeba Energy), Kaori Okoda(Amoeba Energy), Hideharu Amano(Keio Univ.),

[Date]2023-03-01
[Paper #]VLD2022-82,HWS2022-53

Programmable Binary Hyperdimensional Computing Accelerator for Low Power Devices

Yuya Isaka(NAIST), Nau Sakaguchi(SJSU), Michiko Inoue(NAIST), Michihiro Shintani(KIT),

[Date]2023-03-01
[Paper #]VLD2022-76,HWS2022-47

Pass/Fail Threshold Determination Based on Gaussian Process Regression in LSI Test

Daisuke Goeda(KIT), Tomoki Nakamura(SCK), Masuo Kajiyama(SCK), Makoto Eiki(SCK), Michihiro Shintani(KIT),

[Date]2023-03-01
[Paper #]VLD2022-74,HWS2022-45

Routing with cleaning in MEDA biochips

Shiro Chiharu(Ritsumei), Nishikawa hiroki(Osaka), Xiangbo Kong(Ritsumei), Tomiyama Hiroyuki(Ritsumei), Yamashita Shigeru(Ritsumei),

[Date]2023-03-01
[Paper #]VLD2022-84,HWS2022-55

A fast SRAF optimization using Voronoi diagram and LUT based intensity evaluation

Sota Saito(Tokyo Tech), Yu Horimoto(Tokyo Tech), Atsushi Takahashi(Tokyo Tech), Yukihide Kohira(Univ. of Aizu), Chikaaki Kodama(KIOXIA),

[Date]2023-03-01
[Paper #]VLD2022-80,HWS2022-51

A Study on Interface Circuits for Burst Transfers from Synchronous to Asynchronous Circuits

Shogo Semba(UoA), Hiroshi Saito(UoA),

[Date]2023-03-01
[Paper #]VLD2022-78,HWS2022-49

A Deep Reinforcement Learning-based Routing Algorithm for Unknown Erroneous Cells in DMFBs

Tomohisa Kawakami(Ritsumeikan Univ.), Chiharu Shiro(Ritsumeikan Univ.), Hiroki Nishikawa(Osaka Univ.), Kong Xiangbo(Ritsumeikan Univ.), Hiroyuki Tomiyama(Ritsumeikan Univ.), Shigeru Yamashita(Ritsumeikan Univ.),

[Date]2023-03-01
[Paper #]VLD2022-83,HWS2022-54

High fidelity mask pattern generation method by amplitude component evaluation

Yu Horimoto(Tokyo Tech), Sota Saito(Tokyo Tech), Atsushi Takahashi(Tokyo Tech), Yukihide Kohira(Univ. of Aizu), Chikaaki Kodama(KIOXIA),

[Date]2023-03-01
[Paper #]VLD2022-79,HWS2022-50

Acceleration of Memristor Modeling Based on Machine Learning Using Gaussian Process

Yuta Shintani(Naist), Michiko Inoue(Naist), Michihiro Shintani(Kyoto Institute of Technology),

[Date]2023-03-01
[Paper #]VLD2022-75,HWS2022-46

A Feature Vector Considering Characteristics of Optical System for Lithography Hotspot Detection

Masahiro Yamamoto(HCU), Masato Inagi(HCU), Shinobu Nagayama(HCU),

[Date]2023-03-01
[Paper #]VLD2022-81,HWS2022-52

[Memorial Lecture] CNFET7: An Open Source Cell Library for 7-nm CNFET Technology

Chenlin Shi(UEC), Shinobu Miwa(UEC), Tongxin Yang(UOT), Ryota Shioya(UOT), Hayato Yamaki(UEC), Hiroki Honda(UEC),

[Date]2023-03-02
[Paper #]VLD2022-92,HWS2022-63

[Memorial Lecture] An SMT-Solver-based Synthesis of NNA-Compliant antum Circuits Consisting of CNOT, H and T Gates

Kyehei Seino(Ritsumeikan University), Shigeru Yamashita(Ritsumeikan University),

[Date]2023-03-02
[Paper #]VLD2022-94,HWS2022-65

[Memorial Lecture] Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects

Takuma Nagao(NAIST), Tomoki Nakamura(Sony Semiconductor Manufacturing), Masuo Kajiyama(Sony Semiconductor Manufacturing), Makoto Eiki(Sony Semiconductor Manufacturing), Michiko Inoue(NAIST), Michihiro Shintani(Kyoto Institute of Technology),

[Date]2023-03-02
[Paper #]VLD2022-91,HWS2022-62

A Study and an Evaluation of the High Performance Deep Neural Network Inference circuit on FPGAs

Ryo Yamamoto(Mitsubishi Electric), Kenya Sugihara(Mitsubishi Electric), Yoshihiro Ogawa(Mitsubishi Electric),

[Date]2023-03-02
[Paper #]VLD2022-87,HWS2022-58

スマートミュージアムにおけるサーモグラフィを用いた低消費エネルギー人検出システムの開発

Shingo Tetsuka(Univ. of Aizu), Yukihide Kohira(Univ. of Aizu), Rentaro Yoshioka(Univ. of Aizu),

[Date]2023-03-02
[Paper #]VLD2022-85,HWS2022-56

Secure Cache System against On-Chip Threats

Keisuke Kamahori(UTokyo), Shinya Takamaeda(UTokyo),

[Date]2023-03-02
[Paper #]VLD2022-95,HWS2022-66

Communication-Efficient Federated Learning with Gradient Boosting Decision Trees

Kotaro Shimamura(UTokyo), Shinya Takamaeda(UTokyo),