| Presentation | 2023-03-01 Acceleration of Memristor Modeling Based on Machine Learning Using Gaussian Process Yuta Shintani, Michiko Inoue, Michihiro Shintani, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | There has been a great deal of research into the development of domain-specific circuits for multiply-and-accumulate processing, which play a central role in machine learning by interpreting new physical phenomena into computing and storage capabilities. On the other hand, these devices have an unresolved operation principle, and therefore, compact models that are essential for circuit design cannot be created with sufficient accuracy. In this study, we propose a compact modeling method based on Gaussian processes for memristors. Although modeling methods based on machine learning have been proposed in the past, only the accuracy of reproduction by SPICE has been evaluated, and long learning times have not been sufficiently discussed. The proposed method reduces the learning time by using a Gaussian process and also reduces the inference time in SPICE simulation by considering sparsity. Evaluation using data of memristor devices obtained by actual measurements shows that the proposed method is more than 3,239 times faster than existing methods using LSTM (long short-term memory), and that inference on a commercial SPICE simulator can be performed with the same accuracy and computation time. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Compact modeling / Gaussian process regression / Memoristor |
| Paper # | VLD2022-75,HWS2022-46 |
| Date of Issue | 2023-02-22 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2023/3/1(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Makoto Nagata(Kobe Univ.) / Minako Ikeda(NTT) |
| Vice Chair | Yuichi Hayashi(NAIST) / Daisuke Suzuki(Mitsubishi Electric) / Shigetoshi Nakatake(Univ. of Kitakyushu) |
| Secretary | Yuichi Hayashi(Sony Semiconductor Solutions) / Daisuke Suzuki(NAIST) / Shigetoshi Nakatake(NBS) |
| Assistant | / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Acceleration of Memristor Modeling Based on Machine Learning Using Gaussian Process |
| Sub Title (in English) | |
| Keyword(1) | Compact modeling |
| Keyword(2) | Gaussian process regression |
| Keyword(3) | Memoristor |
| 1st Author's Name | Yuta Shintani |
| 1st Author's Affiliation | Nara Institute of Science and Technology(Naist) |
| 2nd Author's Name | Michiko Inoue |
| 2nd Author's Affiliation | Nara Institute of Science and Technology(Naist) |
| 3rd Author's Name | Michihiro Shintani |
| 3rd Author's Affiliation | Kyoto Institute of Technology(Kyoto Institute of Technology) |
| Date | 2023-03-01 |
| Paper # | VLD2022-75,HWS2022-46 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-402,HWS-403 |
| Page | pp.pp.13-18(VLD), pp.13-18(HWS), |
| #Pages | 6 |
| Date of Issue | 2023-02-22 (VLD, HWS) |