Information and Systems-Computer Systems(Date:2013/11/20)

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表紙

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[Date]2013/11/20
[Paper #]
目次

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[Date]2013/11/20
[Paper #]
Circuit design for SD-stacking using TSV interconnects

Kenichi Osada,  Futoshi Furuta,  Kenichi Takeda,  

[Date]2013/11/20
[Paper #]VLD2013-73,CPM2013-117,ICD2013-94,CPSY2013-58,DC2013-39,RECONF2013-41
3D Clock Distribution Using Vertically/Horizontally Coupled Resonators

Yasuhiro Take,  Noriyuki Miura,  Hiroki Ishikuro,  Tadahiro Kuroda,  

[Date]2013/11/20
[Paper #]VLD2013-74,CPM2013-118,ICD2013-95,CPSY2013-59,DC2013-40,RECONF2013-42
Cu Wiring Technology for 3D/2.5D Packaging

Motoaki TANI,  Yoshihiro NAKATA,  Tsuyoshi KANKI,  Tomoji NAKAMURA,  

[Date]2013/11/20
[Paper #]VLD2013-75,CPM2013-119,ICD2013-96,CPSY2013-60,DC2013-41,RECONF2013-43
Chip Thinning Technologies for Chip Stacking Packages

Shinya TAKYU,  Tetsuya KUROSAWA,  

[Date]2013/11/20
[Paper #]VLD2013-76,CPM2013-120,ICD2013-97,CPSY2013-61,DC2013-42,RECONF2013-44
The age of Space Discovery Opened by World's First Solar Sail "IKAROS"

Osamu MORI,  

[Date]2013/11/20
[Paper #]VLD2013-86,CPM2013-120,ICD2013-98,CPSY2013-62,DC2013-52,RECONF2013-45
Toward VLSI Reliability Enhancement by Reconfigurable Architecture

Takao ONOYE,  Masanori HASHIMOTO,  Yukio MITSUYAMA,  Dawood ALNAJJAR,  Hiroaki KONOURA,  

[Date]2013/11/20
[Paper #]VLD2013-87,CPM2013-122,ICD2013-99,CPSY2013-63,DC2013-53,RECONF2013-51
Study of the Hardware Trojan for Embedded Processor

Yasushi TSUKADA,  Shuhei ITAYA,  Takeshi KUMAKI,  OGURA Takeshi /,  Takeshi FUJINO,  

[Date]2013/11/20
[Paper #]CPSY2013-64
Implementation of a fast runtime visualization of a GPU-based electromagnetic simulation using a 3D-FDTD method

Kota AOKI,  Keisuke DOHI,  Yuichiro SHIBATA,  Kiyoshi OGURI,  Takafumi FUJIMOTO,  

[Date]2013/11/20
[Paper #]CPSY2013-65
TinyCSE : Tiny Computer System for Education

Ryosuke NAKAMURA,  Koji NAKANO,  Yasuaki ITO,  

[Date]2013/11/20
[Paper #]CPSY2013-66
A Study on an Optimal Architecture for Stream Mining Applications with FPGA

Sayaka AKIOKA,  

[Date]2013/11/20
[Paper #]CPSY2013-67
A circuit division method for High-Level synthesis on Multi-FPGA systems in stream processing

Daiki KUGAMI,  Takaaki MIYAJIMA,  Hideharu AMANO,  

[Date]2013/11/20
[Paper #]CPSY2013-68
A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs

Md. Nazrul Islam MONDAL,  Kouhan SAI,  Koji NAKANO,  Yasuaki ITO,  

[Date]2013/11/20
[Paper #]CPSY2013-69
A study of multi-port shared cache architecture for a multi-core processor on an FPGA

Hongkun JIN,  Yoshiki YAMAGUCHI,  Yuetsu KODAMA,  

[Date]2013/11/20
[Paper #]CPSY2013-70
NoC routers using the marching memory through type

Ryota YASUDO,  Takahiro KAGAMI,  Hideharu AMANO,  Yasunobu NAKASE,  Masashi WATANABE,  Tsukasa OISHI,  Toru SHIMIZU,  Tadao NAKAMURA,  

[Date]2013/11/20
[Paper #]CPSY2013-71
A 3-D NoC architecture using CSMA/CD bus for inter-chip wireless communication

Takahiro KAGAMI,  Hiroki MATSUTANI,  Michihiro KOIBUCHI,  Hideharu AMANO,  

[Date]2013/11/20
[Paper #]CPSY2013-72
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[Date]2013/11/20
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[Date]2013/11/20
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