Information and Systems-Computer Systems(Date:2002/11/21)

Presentation
表紙

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[Date]2002/11/21
[Paper #]
目次

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[Date]2002/11/21
[Paper #]
Design of Media embedded Processor

Satoshi INOUE,  

[Date]2002/11/21
[Paper #]CPSY2002-51
Design-Manufacturing Interface for .13 um and below

Andrzej Strojwas,  

[Date]2002/11/21
[Paper #]CPSY2002-52
Cycle-Accurate Processor Modeling Written in Java Language

Masatoshi SHIMA,  Arata SHINOZAKI,  Tadashi SATO,  

[Date]2002/11/21
[Paper #]CPSY2002-53
Modeling Single Bus System with Real-time Constraints by Java and Design Methodology using Parametric Model Checking

Tomo KITAGUCHI,  Tadaaki TANIMOTO,  Akio NAKATA,  Teruo HIGASHINO,  

[Date]2002/11/21
[Paper #]CPSY2002-54
Address Bus Energy Optimization via Encoding and Compiler Techniques

Hiroyuki TOMIYAMA,  

[Date]2002/11/21
[Paper #]CPSY2002-55
A front-end for better behavioral synthesis

Lovic Gauthier,  Natasha Devroye,  Hiroyuki Tomiyama,  Kazuaki Murakami,  

[Date]2002/11/21
[Paper #]CPSY2002-56
An Integrated Method of Timing-Driven Floorplanning and Behavioral Synthesis

Shinya YAMASAKI,  Shin'ichi WAKABAYASHI,  

[Date]2002/11/21
[Paper #]CPSY2002-57
A Proposal of Zero Overhead Loop Model in ASIP Meister

Kentaro MITA,  Shinsuke KOBAYASHI,  Yoshinori TAKEUCHI,  Keishi SAKANUSHI,  Masaharu IMAI,  

[Date]2002/11/21
[Paper #]CPSY2002-58
Implementation of Scalable Communication Switches on PCA

Hideyuki TSUBOI,  Tsunemichi SHIOZAWA,  Yuichi OKUYAMA,  Akira NAGOYA,  

[Date]2002/11/21
[Paper #]CPSY2002-59
Fundamental Design of a Parallel Queue Processor

Ben A. ABDERAZEK,  Soichi SHIGETA,  Kirilka NIKOLOVA,  Tsutomu YOSHINAGA,  Masahiro SOWA,  

[Date]2002/11/21
[Paper #]CPSY2002-60
Cache Coherence Management by Adaptive Directory

Toshihide HAGIWARA,  Kiyofumi TANAKA,  

[Date]2002/11/21
[Paper #]CPSY2002-61
An approach to locate of crosspoint faults and stuck-at faults in a PLA block of CPLDs

Wataru OCHIAI,  Toshiyuki TSUTSUMI,  Koji YAMAZAKI,  Kazutaka TOMIZAWA,  

[Date]2002/11/21
[Paper #]CPSY2002-62
On acceleration methods of equivalence checking

Yusuke MATSUNAGA,  

[Date]2002/11/21
[Paper #]CPSY2002-63
Debug Methodology for Arithmetic Circuits

Masao KUBO,  Masahiro FUJITA,  

[Date]2002/11/21
[Paper #]CPSY2002-64
Test data volume reduction using statistical encoding for multiple scan chain designs

Kenjiro Taniguchi,  Kohei Miyase,  Seiji Kajihara,  Irith Pomeranz,  Sudhakar M. Reddy,  

[Date]2002/11/21
[Paper #]CPSY2002-65
Statistical Gate-Delay Modeling with Intra-gate Variability

Kenichi OKADA,  Kento YAMAOKA,  Hidetoshi ONODERA,  

[Date]2002/11/21
[Paper #]CPSY2002-66
Control Signal Sharing of Asynchronous Circuits Using Datapath Delay Information

Hiroshi SAITO,  Euiseok KIM,  Masashi IMAI,  Nattha SRETASEREEKUL,  Hiroshi NAKAMURA,  Takashi NANYA,  

[Date]2002/11/21
[Paper #]CPSY2002-67
Multi-Cycle Path Analysis Considering Multi-Phase Clocks

Hiroyuki HIGUCHI,  

[Date]2002/11/21
[Paper #]CPSY2002-68
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