Information and Systems-Computer Systems(Date:1997/01/29)

Presentation
表紙

,  

[Date]1997/1/29
[Paper #]
目次

,  

[Date]1997/1/29
[Paper #]
Implementation and Evaluation of the Multi-job EULASH Kernel for Efficient use of Local memory

Y. Yamaguchi,  H. Kitoh,  J. Yamamoto,  H. Amano,  

[Date]1997/1/29
[Paper #]CPSY96-99
A Fine Grain Protection Mechanism using a Cache Line as a Protection Unit

Noritaka OSAWA,  Toshitsugu YUBA,  

[Date]1997/1/29
[Paper #]CPSY96-100
On-Chip-Multiprocessing Architecture :Memory System

Takeshi SANO,  Toshitaka KUMAGAI,  Keizo SAISHO,  Akira FUKUDA,  

[Date]1997/1/29
[Paper #]CPSY96-101
(Mπ)^2 : A massively parallel processing system for image synthesis with a distributed frame buffer system

Takauki Maeda,  Hitoshi Yamauchi,  Hiroaki Kobayashi,  Tadao Nakamura,  

[Date]1997/1/29
[Paper #]CPSY96-102
An implementation of cache control mechanism for MIN based multiprocessors

T. Kamei,  T. Hanawa,  K. Nishimura,  H. Amano,  

[Date]1997/1/29
[Paper #]CPSY96-103
Fault-Tolerant Meshes with Efficient Layouts

Toshinori Yamada,  Shuichi Ueno,  

[Date]1997/1/29
[Paper #]CPSY96-104
Implementation of a large Petri Net by a group of Petri Net Controllers

Tstsuya Kamakura,  Teruaki Shimoda,  Hideki Murakoshi,  Yasunori Dohi,  

[Date]1997/1/29
[Paper #]CPSY96-105
Petri Net based High Speed Controller for FA Systems

Yuji TAKEDA,  Hideki MURAKOSHI,  Noboru FUNAKUBO,  Yasunori DOHI,  

[Date]1997/1/29
[Paper #]CPSY96-106
A Macro Task scheduling Method of Overlapping of Data Transfer and Task Processing

Shigeru HASHIMOTO,  Kensaku FUJIMOTO,  Masami OKAMOTO,  Hironori KASAHARA,  

[Date]1997/1/29
[Paper #]CPSY96-107
[OTHERS]

,  

[Date]1997/1/29
[Paper #]