Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2013/05/09)

Presentation
表紙

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[Date]2013/5/9
[Paper #]
目次

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[Date]2013/5/9
[Paper #]
Performance-driven SRAM Macro Design with Parameterized Cell Considering Layout-dependent Effects

Yu ZHANG,  Shigetoshi NAKATAKE,  

[Date]2013/5/9
[Paper #]VLD2013-1
A Floorplan Method by Simulated Annealing and Sequence-pair for Asynchronous Circuits with Bundled-data Implementation

Minoru IIZUKA,  Hiroshi SAITO,  

[Date]2013/5/9
[Paper #]VLD2013-2
A Longest Path Algorithm for Differential Pair Net Considering Connectivity

Koji YAMAZAKI,  Yukihide KOHIRA,  

[Date]2013/5/9
[Paper #]VLD2013-3
An Automatic Rectifying Method for Large-Scale Circuit with Programmable Devices

SATOSHI JO,  TAKESHI MATSUMOTO,  MASAHIRO FUJITA,  

[Date]2013/5/9
[Paper #]Vol.2013-SLDM-161 No.4
A Debugging Method for Gate Level Circuit with Programmable Devices

KOSUKE OSHIMA,  SATOSHI JO,  TAKESHI MATSUMOTO,  MASAHIRO FUJITA,  

[Date]2013/5/9
[Paper #]Vol.2013-SLDM-161 No.5
Microarchitecture Verification using CTL Deduction system

Yuji Yamada,  Ryota Tomioka,  Ryuichi Takahashi,  

[Date]2013/5/9
[Paper #]Vol.2013-SLDM-161 No.6
A Note on Routing and Placement

Yoji KAJITANI,  

[Date]2013/5/9
[Paper #]VLD2013-4
Level Converter Design for Ultra Low Voltage Operation in Silicon-on-Thin-BOX MOSFET

Shohei NAKAMURA,  Kimiyoshi USAMI,  

[Date]2013/5/9
[Paper #]VLD2013-5
A Linear Interpolation Unit Using Selector Logics

Masashi SHIO,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2013/5/9
[Paper #]VLD2013-6
Data Dependence Relaxation Techniques for Reducing Iteration Intervals in Pipelined Loops

Shingo KUSAKABE,  Kenshu SETO,  

[Date]2013/5/9
[Paper #]VLD2013-7
Scan-based Attack against Trivium Stream Cipher Using Scan Signatures

Mika FUJISHIRO,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2013/5/9
[Paper #]VLD2013-8
A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures

Kazushi KAWAMURA,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2013/5/9
[Paper #]VLD2013-9
SoC System Design Methodology with Fully-Coherent Cache

Kodai MORITAKA,  Hiroaki YOSHIDA,  Mitsuru TOMONO,  Yasuhiko NAKASHIMA,  

[Date]2013/5/9
[Paper #]VLD2013-10
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[Date]2013/5/9
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[Date]2013/5/9
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[Date]2013/5/9
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[Date]2013/5/9
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