Presentation | 2013-05-16 Performance-driven SRAM Macro Design with Parameterized Cell Considering Layout-dependent Effects Yu ZHANG, Shigetoshi NAKATAKE, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In nano-scale process, shallow trench isolation (STI) stress and well proximity effect (WPE) affect the threshold voltage of MOSFET as well as the performance of the system-on-chips (SoC). As one of the most sensitive and highest density circuit, SRAMs must be designed considering the stress effect analysis. The variation of the stress effect causes dramatical change of the threshold voltage especially beyond 90nm process. In this paper, we present an SRAM macro design methodology dealing with a significant trade-off among area, leakage power and delay by introducing non-uniform parameterized SRAM cells. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | SRAM / STI / WPE / leakage power / delay / area |
Paper # | VLD2013-1 |
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Committee | VLD |
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Conference Date | 2013/5/9(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Performance-driven SRAM Macro Design with Parameterized Cell Considering Layout-dependent Effects |
Sub Title (in English) | |
Keyword(1) | SRAM |
Keyword(2) | STI |
Keyword(3) | WPE |
Keyword(4) | leakage power |
Keyword(5) | delay |
Keyword(6) | area |
1st Author's Name | Yu ZHANG |
1st Author's Affiliation | School of Environmental Engineering, The University of Kitakyushu() |
2nd Author's Name | Shigetoshi NAKATAKE |
2nd Author's Affiliation | Department of Information and Media Engineering, the University of Kitakyushu |
Date | 2013-05-16 |
Paper # | VLD2013-1 |
Volume (vol) | vol.113 |
Number (no) | 30 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |