Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2010/09/20)

Presentation
表紙

,  

[Date]2010/9/20
[Paper #]
目次

,  

[Date]2010/9/20
[Paper #]
Ordered Coloring for Skew-Adjustability-Aware Resource Binding

Mineo KANEKO,  

[Date]2010/9/20
[Paper #]VLD2010-42
Accelerator-Centric Task Allocation Based on Algorithm Transformation for Heterogeneous Multicore Processors

Masanori HARIYAMA,  WAIDYASOORIYA Hasitha MUTHUMALA,  Michitaka KAMEYAMA,  

[Date]2010/9/20
[Paper #]VLD2010-43
Design and Evaluation of Arbiter Physical Unclonable Functions

Kota FURUHASHI,  Mitsuru SHIOZAKI,  Akitaka FUKUSHIMA,  Takahiko MURAYAMA,  Takeshi FUJINO,  

[Date]2010/9/20
[Paper #]VLD2010-44
Analog Circuit Optimization Using Pareto-Optimality

Yu LIU,  Masato YOSHIOKA,  Katsumi HOMMA,  Yuji KANAZAWA,  Toshiyuki SHIBUYA,  

[Date]2010/9/20
[Paper #]VLD2010-45
An Automatic Test Generation Framework for Digitally-Assisted Analog Circuit

Satoshi KOMATSU,  Mohamed ABBAS,  Yasuo FURUKAWA,  Kunihiro ASADA,  

[Date]2010/9/20
[Paper #]VLD2010-46
Length-Matching Routing on Single Layer for PCB Routing Design

Yukihide KOHIRA,  Atsushi TAKAHASHI,  

[Date]2010/9/20
[Paper #]VLD2010-47
A Method of Analog IC Placement with Common Centroid Constraints

Keitaro UE,  Kunihiro FUJIYOSHI,  

[Date]2010/9/20
[Paper #]VLD2010-48
Analog Layout Retargeting with Constraint Extraction by Matching of Fundamental Circuit Components and Layout Regularity

Kazuhiko SHIBATA,  Shigetoshi NAKATAKE,  

[Date]2010/9/20
[Paper #]VLD2010-49
Regularity-Oriented Compaction with Z-Cut Perturbation

Shigetoshi NAKATAKE,  

[Date]2010/9/20
[Paper #]VLD2010-50
Fast Optimization on Minimum Perturbation Placement Realization

Yuki KOUNO,  Yasuhiro TAKASHIMA,  Atsushi TAKAHASHI,  

[Date]2010/9/20
[Paper #]VLD2010-51
Application of Ultra Low-power Circuit Techniques to Wireless Terminals in Wide Area Ubiquitous Network : Approach to Nano-watt Wireless Sensor Nodes

Yuichi KADO,  Mitsuru HARADA,  Mamoru UGAJIN,  Akihiro YAMAGISHI,  Mitsuo NAKAMURA,  

[Date]2010/9/20
[Paper #]VLD2010-52
A study of temperature characteristics of ring-oscillator based threshold voltage estimation

Takumi UEZONO,  Hiroyuki OCHI,  Takashi SATO,  

[Date]2010/9/20
[Paper #]VLD2010-53
Analysis and Evaluation of Simultaneous Switching Noise of FPGA

Yo Takahashi,  Toshio Sudo,  Kunio Ota,  Kazuhisa Matuge,  

[Date]2010/9/20
[Paper #]VLD2010-54
Measurement Circuits for Acquiring SET PulseWidth Distribution with Fine Time Resolution

Ryo HARADA,  Yukio MITSUYAMA,  Masanori HASHIMOTO,  Takao ONOYE,  

[Date]2010/9/20
[Paper #]VLD2010-55
Modeling of Latching Probability of Soft-Error-Induced Pulse

Motoharu HIRATA,  Masayoshi YOSHIMURA,  Yuusuke MATSUNAGA,  

[Date]2010/9/20
[Paper #]VLD2010-56
複写される方へ

,  

[Date]2010/9/20
[Paper #]
奥付

,  

[Date]2010/9/20
[Paper #]
裏表紙

,  

[Date]2010/9/20
[Paper #]