| Presentation | 2010-09-27 Accelerator-Centric Task Allocation Based on Algorithm Transformation for Heterogeneous Multicore Processors Masanori HARIYAMA, WAIDYASOORIYA Hasitha MUTHUMALA, Michitaka KAMEYAMA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Heterogeneous multi-core processors are attracted by the media processing applications due to their capability of drawing strengths of different cores to improve the overall performance. However, the data transfer bottlenecks and limitations in the task allocation due to the accelerator-incompatible operations prevents us from gaining full potential of the heterogeneous multi-core processors. This paper presents a task allocation method based on algorithm transformation to increase the freedom of task allocation. We use approximation methods such as CORDIC algorithms to map the accelerator-incompatible operations to accelerator cores. According to the experimental results using HOG descriptor computation, the proposed task allocation method reduces the data transfer time by more than 82% and the total processing time by more than 79% compared to the conventional task allocation method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Heterogeneous multi-core processor / task-allocation / accelerator / reconfigurable architecture |
| Paper # | VLD2010-43 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2010/9/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Accelerator-Centric Task Allocation Based on Algorithm Transformation for Heterogeneous Multicore Processors |
| Sub Title (in English) | |
| Keyword(1) | Heterogeneous multi-core processor |
| Keyword(2) | task-allocation |
| Keyword(3) | accelerator |
| Keyword(4) | reconfigurable architecture |
| 1st Author's Name | Masanori HARIYAMA |
| 1st Author's Affiliation | Graduate School of Information Sciences, Tohoku University() |
| 2nd Author's Name | WAIDYASOORIYA Hasitha MUTHUMALA |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Michitaka KAMEYAMA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 2010-09-27 |
| Paper # | VLD2010-43 |
| Volume (vol) | vol.110 |
| Number (no) | 210 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |