Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2004/03/04)

Presentation
表紙

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[Date]2004/3/4
[Paper #]
目次

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[Date]2004/3/4
[Paper #]
Analytical Delay Model Equations for CMOS Inverter Based on Velocity Saturation Effect

Takashi Tsutsumi,  Toshiro Akino,  

[Date]2004/3/4
[Paper #]VLD2003-136
High resolution measurements of power-supply and well noises in digital integrated circuits

Takeshi OKUMOTO,  Makoto NAGATA,  Kenji SHIMAZAKI,  Shozo HIRANO,  Hiroyuki TSUJIKAWA,  

[Date]2004/3/4
[Paper #]VLD2003-137
Handling Soft Modules in General Floorplan

Hiroaki ITOGA,  Kunihiro FUJIYOSHI,  

[Date]2004/3/4
[Paper #]VLD2003-138
Design, Fabrication and Performance of a High-Speed, Low Stand-by Power SRAM Incorporating a Self-controllable Voltage Level (SVL) Circuit

Yuki Higuchi,  Yoshinori Oka,  Tadayoshi Enomoto,  

[Date]2004/3/4
[Paper #]VLD2003-139
The Method to Construct Clock Tree with Low Power Consumption

Akihiko MORIYA,  Atsushi TAKAHASHI,  

[Date]2004/3/4
[Paper #]VLD2003-140
Reduction of peak power in LSI by using semi-synchronous circuit design

Soji MORI,  Atsushi TAKAHASHI,  

[Date]2004/3/4
[Paper #]VLD2003-141
A Logic Synthesis Methodology for High Speed Logic Technology ASDDL/ASD-CMOS

Yoshinori TANAKA,  Masao MORIMOTO,  Makoto NAGATA,  Kazuo TAKI,  

[Date]2004/3/4
[Paper #]VLD2003-142
Static Timing Analysis Considering Supply Voltage Variation among Logic Cells

Junji YAMAGUCHI,  Masanori HASHIMOTO,  Hidetoshi ONODERA,  

[Date]2004/3/4
[Paper #]VLD2003-143
Technological Trend of Microprocessors for Mobile Multimedia

Kunio UCHIYAMA,  

[Date]2004/3/4
[Paper #]VLD2003-144
A Netowork Processor Synthesis System

Tsutomu MATSUURA,  Jumpei UCHIDA,  Yuichiro MIYAOKA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2004/3/4
[Paper #]VLD2003-145
An Efficient Equivalence Checking Method for C Descriptions Based on Textual Differences

Takeshi MATSUMOTO,  Hiroshi SAITO,  Masahiro FUJITA,  

[Date]2004/3/4
[Paper #]VLD2003-146
A Case Study on Behavioral Synthesis of an Automotive Engine Control Circuit

Yoshiyuki SUZUKI,  Takayuki NATSUME,  Shinya HONDA,  Shinichi IIYAMA,  Hiroyuki TOMIYAMA,  Hiroaki TAKADA,  Ryuji OKAMURA,  Shigeru SASAKI,  

[Date]2004/3/4
[Paper #]VLD2003-147
Verification of the Eric Processor Specification using the Spec language

Youji KUWAYAMA,  Kenta NAKAMURA,  Muneyuki HARADA,  Hiroaki HONDA,  kazuaki MURAKAMI,  

[Date]2004/3/4
[Paper #]VLD2003-148
A Program Slicing for System Level Description written in SpecC Language

Ken TANABE,  Hiroshi SAITO,  Satoshi KOMATSU,  Masahiro FUJITA,  

[Date]2004/3/4
[Paper #]VLD2003-149
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[Date]2004/3/4
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[Date]2004/3/4
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