| Presentation | 2004/3/4 Reduction of peak power in LSI by using semi-synchronous circuit design Soji MORI, Atsushi TAKAHASHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The reduction of peak power consumption is required to reduce the instability of gate operation, the delay increase and the noise etc. The purpose of this paper is to reduce this peak power by using semi-synchronous framework. First, this paper proposes a fast power estimation method. Second, a clock scheduling method to reduce peak power which uses the proposed power estimation method is proposed. The validity of proposed method is shown by spice level simulation in which complete synchronous circuit, semi-synchronous circuit with distributed clock schedule that achieves minimum clock period, and semi-synchronous circuit with clock-schedule obtained by the proposed method are compared. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | semi-synchronous circuit / peak powr / sequential logic circuit |
| Paper # | VLD2003-141 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2004/3/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reduction of peak power in LSI by using semi-synchronous circuit design |
| Sub Title (in English) | |
| Keyword(1) | semi-synchronous circuit |
| Keyword(2) | peak powr |
| Keyword(3) | sequential logic circuit |
| 1st Author's Name | Soji MORI |
| 1st Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology() |
| 2nd Author's Name | Atsushi TAKAHASHI |
| 2nd Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
| Date | 2004/3/4 |
| Paper # | VLD2003-141 |
| Volume (vol) | vol.103 |
| Number (no) | 702 |
| Page | pp.pp.- |
| #Pages | 6 |
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