Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1999/03/03)

Presentation
表紙

,  

[Date]1999/3/3
[Paper #]
正誤表

,  

[Date]1999/3/3
[Paper #]
目次

,  

[Date]1999/3/3
[Paper #]
SPT-SA : A Staradard-Cell Placemnent Optimizatiorn usirng Simulated Annealing by the Phase Transition Tenperature

Noriko Ishibashi,  Keiichi Kurokawa,  Masahiko Toyonaga,  

[Date]1999/3/3
[Paper #]VLD98-131
Timing-driven placement with buffer-insertion and gate-sizing

Mitsuru Tagata,  Takumi Okamoto,  Kazushi Nakamura,  Shigeyoshi Tawada,  

[Date]1999/3/3
[Paper #]VLD98-132
Transistor Size and Folding Optimization Method

Masakazu Tanaka,  Masahiro Fukui,  

[Date]1999/3/3
[Paper #]VLD98-133
A Consideration on a Routing Problem to Minimize the Weighted Sum of Elmore Delays

Naofumi Tsujii,  Katsutoshi Baba,  Shuji Tsukiyama,  

[Date]1999/3/3
[Paper #]VLD98-134
Steiner Routing Based on Elmore Delay Model

Tadao Kadodi,  Satoshi Tayu,  Mineo Kaneko,  

[Date]1999/3/3
[Paper #]VLD98-135
On Bus Architecture Design Considering Crosstalk

Kei HIROSE,  Hiroto YASUURA,  

[Date]1999/3/3
[Paper #]VLD98-136
A Delay Calculator System for Deep Submicron Design

Takayuki Ohshima,  Toshiyuki Saito,  Yoko Fujita,  Yukio Minoda,  Takashi Nakaya,  

[Date]1999/3/3
[Paper #]VLD98-137
A Realization of Cycle-based Simulation Engine using Decision Diagrams

Atsumu ISENO,  Yukihiro IGUCHI,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]1999/3/3
[Paper #]VLD98-138
A Design Verification for the Arithmetie Logical Unit by using a Proof Cheker

Katsumi WASAKI,  Yasushi FUWA,  Yatsuka NAKAMURA,  Yasunari SHIMADA,  

[Date]1999/3/3
[Paper #]VLD98-139
Hardware Model Based Evaluation of Irredundant Full Search Motion Estimation

Katsumi TAKAYAMA,  Shogo MURAMATSU,  Hitoshi KIYA,  Akihiko YAMADA,  

[Date]1999/3/3
[Paper #]VLD98-140
[OTHERS]

,  

[Date]1999/3/3
[Paper #]