| Presentation | 1999/3/3 Timing-driven placement with buffer-insertion and gate-sizing Mitsuru Tagata, Takumi Okamoto, Kazushi Nakamura, Shigeyoshi Tawada, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a new timing-driven placement method of automatic layout system GALET. We have developed a new timing-driven placement algorithm, that is combined with buffer-insertion and gate-sizeing.In our experiments, performance improvement have been obtained for high performance deep-submicron LSI byour proposed method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | timing driven / automatic placement / buffer insertion / gate sizing / path delay constraint |
| Paper # | VLD98-132 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1999/3/3(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Timing-driven placement with buffer-insertion and gate-sizing |
| Sub Title (in English) | |
| Keyword(1) | timing driven |
| Keyword(2) | automatic placement |
| Keyword(3) | buffer insertion |
| Keyword(4) | gate sizing |
| Keyword(5) | path delay constraint |
| 1st Author's Name | Mitsuru Tagata |
| 1st Author's Affiliation | NEC Software Hokuriku,Ltd.() |
| 2nd Author's Name | Takumi Okamoto |
| 2nd Author's Affiliation | NEC Corporation |
| 3rd Author's Name | Kazushi Nakamura |
| 3rd Author's Affiliation | NEC Corporation |
| 4th Author's Name | Shigeyoshi Tawada |
| 4th Author's Affiliation | NEC Software Hokuriku,Ltd. |
| Date | 1999/3/3 |
| Paper # | VLD98-132 |
| Volume (vol) | vol.98 |
| Number (no) | 624 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |