Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1997/12/12)

Presentation
表紙

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[Date]1997/12/12
[Paper #]
目次

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[Date]1997/12/12
[Paper #]
A Reconstructable System for Telecommunications

Toshiaki Miyazaki,  Kazuhiro Shirakawa,  Masaru Katayama,  Takahiro Murooka,  Atsushi Takahara,  Kazuhiro Hayashi,  

[Date]1997/12/12
[Paper #]VLD97-100
Hardware Resource Management on Computer Systems with Reconfigurable Hardware

Yasufumi Itoh,  Shinji Kimura,  Katsumasa Watanabe,  

[Date]1997/12/12
[Paper #]VLD97-101
Programmable ATM Adapter for ATM network using custom FPGAs

Kazuhiro SHIRAKAWA,  Kan TOYOSHIMA,  Kazuhiro HAYASHI,  

[Date]1997/12/12
[Paper #]VLD97-102
A Note on the FPGA Training System and Course Design for the VLSI Design Seminar

Naohiko Shimizu,  Masahiro Yoshida,  Izumi Noma,  

[Date]1997/12/12
[Paper #]VLD97-103
A Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Topology LUTs

Koji ARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]1997/12/12
[Paper #]VLD97-104
A New Method to Express Functional Permissibilities and Its Application to FPGA Synthesis

Shigeru Yamashita,  Hiroshi Sawada,  Akira Nagoya,  

[Date]1997/12/12
[Paper #]VLD97-105
A Consideration on Pass Transistor Logic Circuit Design by a BDD Decomposition

Hidekazu Kanaya,  Shuji Tsukiyama,  

[Date]1997/12/12
[Paper #]VLD97-106
Reconfigurable Parallel ULSI/WSI Processors for Control of Intelligent Robot

Nobuhiro TOMABECHI,  Yoshichika FUJIOKA,  

[Date]1997/12/12
[Paper #]VLD97-107
A Routing Algorithm for WDM Ring

X. Dong,  T. Kudoh,  H. Amano,  

[Date]1997/12/12
[Paper #]VLD97-108
A Practical Row Interchanging Algorithm for Hierarchically Constructed Circuit Matrices using Modified Nodal Analysis

Takashi Sato,  Mikako Miyama,  Goichi Yokomizo,  Kojiro Niho,  

[Date]1997/12/12
[Paper #]VLD97-109
A design of Multiprocessor Simulator Library

M. Wakabayashi,  T. Komeda,  H. Amano,  

[Date]1997/12/12
[Paper #]VLD97-110
Operation Slot Optimization for VLIW Processor

Norimasa Ohtsuki,  Yoshinori Takeuchi,  Masaharu Imai,  Kiyoharu Hamaguchi,  Toshinobu Kashiwabara,  Nobuyuki Hikichi,  

[Date]1997/12/12
[Paper #]VLD97-111
Register-to-Register Data Transfer Optimization in Loop Folding Scheduling

Hiroki TASHIMA,  Kastumi HARASHIMA,  Kunio FUKUNAGA,  

[Date]1997/12/12
[Paper #]VLD97-112
[OTHERS]

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[Date]1997/12/12
[Paper #]