| Presentation | 1997/12/12 A Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Topology LUTs Koji ARA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a technology mapping algorithm for FPGAs whose logic-block includes tree-topology LUTs. The objective of the algorithm is minimizing the number of logic-blocks. First, if an input Boolean network is tree, we propose a linear-time technology mapping algorithm for computing an optimal solution in terms of the number of logic-blocks, Second, the algorithm is extended so that it can be applied to directed acyclic graph. The extended algorithm consists of three steps; i) partition of an input Boolean network at nodes with multiple fanouts into a forest of trees, ii) generation of an optimal solution for each tree, and iii) optimization of the entire Boolean network. The experimental results for several benchmark circuits show its efficiency and effectiveness. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / LUT / technology mapping / tree topology / partition / merge / refine |
| Paper # | VLD97-104 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1997/12/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Topology LUTs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | LUT |
| Keyword(3) | technology mapping |
| Keyword(4) | tree topology |
| Keyword(5) | partition |
| Keyword(6) | merge |
| Keyword(7) | refine |
| 1st Author's Name | Koji ARA |
| 1st Author's Affiliation | Dept. of Electronics, Information and Communication Engineering() |
| 2nd Author's Name | Nozomu TOGAWA |
| 2nd Author's Affiliation | Dept. of Electronics, Information and Communication Engineering |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Dept. of Electronics, Information and Communication Engineering |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Dept. of Electronics, Information and Communication Engineering |
| Date | 1997/12/12 |
| Paper # | VLD97-104 |
| Volume (vol) | vol.97 |
| Number (no) | 444 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |