Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1995/12/15)

Presentation
表紙

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[Date]1995/12/15
[Paper #]
目次

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[Date]1995/12/15
[Paper #]
A New Low-Power Circuit Technology based on Pass-Transistor Logic

BuYeol LEE,  Kazuo TAKI,  

[Date]1995/12/15
[Paper #]VLD95-115
Some Experimental Results on Low Power Design with Gated Clock

Tohru ISHIHARA,  Hiroto YASUURA,  

[Date]1995/12/15
[Paper #]VLD95-116
PERFORMANCE EVALUATION OF FAST DRAMS ON MULTIPROCESSOR SYSTEMS

Tomoyoshi Ueyama,  Kazuaki Ayada,  Kouji Nishimura,  Reji Aibara,  

[Date]1995/12/15
[Paper #]VLD95-117
A Feasibility Study for Design Education Using 32bit RISC Microprocessor DLX-FPGA

Kouji Inoue,  Masahiro Iida,  Masahide Ouchi,  Morihiro Kuga,  Toshinori Sueyoshi,  

[Date]1995/12/15
[Paper #]VLD95-118
The architecture of a SIMD machine with virtual processor

Takahashi HIDEKI,  Masaharu IMAI,  Akichika SHIOMI,  Kunio HONSAWA,  

[Date]1995/12/15
[Paper #]VLD95-119
Observations on the Implementation of a Codesign Workbench PEAS-III for ASIP Design : Classification and Parameterization of CPU Architectures

Kenji Kataoka,  Akichika Shiomi,  Masaharu Imai,  Yoshihiro Aoyama,  Jun Sato,  Nobuyuki Hikichi,  

[Date]1995/12/15
[Paper #]VLD95-120
Hardware/Software Co-design system

Mitsuteru Yukishita,  Akira Nagoya,  Yasufumi Itoh,  Shinji Kimura,  

[Date]1995/12/15
[Paper #]VLD95-121
A Code Placement Technique to Maximize Hit Ratios of Instruction Caches

Hiroyuki TOMIYAMA,  Hiroto YASUURA,  

[Date]1995/12/15
[Paper #]VLD95-122
A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines

Hiroyuki HIGUCHI,  Yusuke MATSUNAGA,  

[Date]1995/12/15
[Paper #]VLD95-123
Parallelization of Dynamic Variable Ordering of BDD Packages

Hiroyuki OCHI,  

[Date]1995/12/15
[Paper #]VLD95-124
Improved Subdivision for Placement

NAOYUKI ISO,  TOMIO HIRATA,  

[Date]1995/12/15
[Paper #]VLD95-125
Two Graphs for Efficient Routability Checking

YASUSHI KAWAGUCHI,  NAOYUKI ISO,  TOMIO HIRATA,  

[Date]1995/12/15
[Paper #]VLD95-126
A Parallel Timing Driven Standard Cell Placement Method with Nonlinear Programming

Mitsuhiro ONO,  Tetsushi KOIDE,  Yutaka Nishimaru,  Shin'ichi WAKABAYASHI,  Noriyoshi YOSHIDA,  

[Date]1995/12/15
[Paper #]VLD95-127
Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC processor Design

Hidekazu Terai,  Kazutoshi Gemma,  Yohsuke Nagao,  Yasuo Satoh,  

[Date]1995/12/15
[Paper #]VLD95-128
[OTHERS]

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[Date]1995/12/15
[Paper #]