| Presentation | 1995/12/15 Two Graphs for Efficient Routability Checking YASUSHI KAWAGUCHI, NAOYUKI ISO, TOMIO HIRATA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In VLSI and printed wiring board design, a routing method consisting of two stages: global routing and detailed routing has been proposed. In such a method, it is necessary to decide the routability, that is, to decide whether the obtained global routing sketch can be transformed into a detailed routing or not. We can decide it by comparing "capacity" and "flow" for each "cut". In this paper, we propose two graphs for efficient routability checking. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | |
| Paper # | VLD95-126 |
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| Committee | VLD |
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| Conference Date | 1995/12/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Two Graphs for Efficient Routability Checking |
| Sub Title (in English) | |
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| 1st Author's Name | YASUSHI KAWAGUCHI |
| 1st Author's Affiliation | Faculty of Engineering, Nagoya University() |
| 2nd Author's Name | NAOYUKI ISO |
| 2nd Author's Affiliation | Faculty of Engineering, Nagoya University |
| 3rd Author's Name | TOMIO HIRATA |
| 3rd Author's Affiliation | Faculty of Engineering, Nagoya University |
| Date | 1995/12/15 |
| Paper # | VLD95-126 |
| Volume (vol) | vol.95 |
| Number (no) | 421 |
| Page | pp.pp.- |
| #Pages | 6 |
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