Engineering Sciences/NOLTA-Reliability(Date:2020/01/22)

Presentation
Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks

Ryosuke Kuramochi(Titech),  Youki Sada(Titech),  Masayuki Shimoda(Titech),  Shimpei Sato(Titech),  Hiroki Nakahara(Titech),  

[Date]2020-01-22
[Paper #]VLD2019-65,CPSY2019-63,RECONF2019-55
Increasing Test Variation for C Compilers by Equivalent Mutant Generation

Hiroki Maeda(Kwansei Gakuin Univ.),  Nagisa ishiura(Kwansei Gakuin Univ.),  

[Date]2020-01-22
[Paper #]VLD2019-61,CPSY2019-59,RECONF2019-51
A Comparison of Filter for Convolutional Neural Network towards Hardware Implementation

Kosuke Akimoto(Tokyo Tech),  Youki Sada(Tokyo Tech),  Shimpei Sato(Tokyo Tech),  Hiroki Hakahara(Tokyo Tech),  

[Date]2020-01-22
[Paper #]VLD2019-64,CPSY2019-62,RECONF2019-54
Implementation and Evaluation of a Router on a Multi-FPGA System

Tomoki Shimizu(Keio Univ.),  Kohei Ito(Keio Univ.),  Kensuke Iizuka(Keio Univ.),  Yugo Yamauchi(Keio Univ.),  Kazuei Hironaka(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2020-01-22
[Paper #]VLD2019-59,CPSY2019-57,RECONF2019-49
Performance Evaluation of Using Multi-Switch on a Multi-FPGA System

Kohei Ito(Keio Univ.),  Kensuke Iizuka(Keio Univ.),  Yugo Yamauchi(Keio Univ.),  Kazuei Hironaka(Keio Univ.),  Yao Hu(NII),  Michihiro Koibuchi(NII),  Hideharu Amano(Keio Univ.),  

[Date]2020-01-22
[Paper #]VLD2019-60,CPSY2019-58,RECONF2019-50
On logic locking method with affine transformation

Yusuke Matsunaga(Kyushu Univ.),  

[Date]2020-01-22
[Paper #]VLD2019-63,CPSY2019-61,RECONF2019-53
最小直径ネットワークトポロジのラック配置最適化

Ryuta Kawano(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  Michihiro Koibuchi(NII),  Hideharu Amano(Keio Univ.),  

[Date]2020-01-22
[Paper #]VLD2019-58,CPSY2019-56,RECONF2019-48
CLAHEの低価格Zynqボードを用いた高位合成による実装

Honda Koki(Keio Univ.),  Wei Kaijie(Keio Univ.),  Arai Masatoshi(Saitama Univ.),  Amano Hideharu(Keio Univ.),  

[Date]2020-01-22
[Paper #]VLD2019-54,CPSY2019-52,RECONF2019-44
Mutation Fuzzing Based on Type Estimation of Data Items Utilizing Data Writer

Yoko Higuchi(Kwansei Gakuin Univ.),  Nagisa Ishiura(Kwansei Gakuin Univ.),  Namba Noriyuki(Kwansei Gakuin Univ.),  

[Date]2020-01-22
[Paper #]VLD2019-62,CPSY2019-60,RECONF2019-52
An FPGA Implementation of Monocular Depth Estimation

Youki Sada(titech),  Masayuki Shimoda(titech),  Shimpei Sato(titech),  Hiroki Nakahara(titech),  

[Date]2020-01-22
[Paper #]VLD2019-66,CPSY2019-64,RECONF2019-56
Task offloading from vector processor to FPGA through PCIe connection

Kohei Hijikata(Tohoku Univ.),  Tomohiro Ueno(RIKEN),  Ryusuke Egawa(Tohoku Univ.),  Hiroyuki Takizawa(Tohoku Univ.),  Kentaro Sano(RIKEN),  

[Date]2020-01-22
[Paper #]VLD2019-55,CPSY2019-53,RECONF2019-45
A Consideration of NAT Traversal Function for MPI Runtime Environment on Android OS

Masahiro Nissato(Utsunomiya Univ.),  Kanemitsu Ootsu(Utsunomiya Univ.),  Takashi Yokota(Utsunomiya Univ.),  

[Date]2020-01-22
[Paper #]VLD2019-57,CPSY2019-55,RECONF2019-47
DDR4 SDRAM controller for real-time processing

So Haramura(Keio Univ.),  Nobuyuki Yamasaki(Keio Univ.),  

[Date]2020-01-22
[Paper #]VLD2019-56,CPSY2019-54,RECONF2019-46
Design and implementation of a RISC-V computer system running Linux in Verilog HDL

Junya Miura(Tokyo Tech),  Hiromu Miyazaki(Tokyo Tech),  Kenji Kise(Tokyo Tech),  

[Date]2020-01-23
[Paper #]VLD2019-72,CPSY2019-70,RECONF2019-62
Design and implementation of a RISC-V soft processor adopting five-stage pipelining

Hiromu Miyazaki(Tokyo Tech),  Takuto Kanamori(Tokyo Tech),  Md Ashraful Islam(Tokyo Tech),  Kenji Kise(Tokyo Tech),  

[Date]2020-01-23
[Paper #]VLD2019-73,CPSY2019-71,RECONF2019-63
FPGA-based Stream Data Aggregation for Large Sliding-Windows

Masaki Osaka(UEC),  Masato Yoshimi(TIS),  Celimuge Wu(UEC),  Tsutomu Yoshinaga(UEC),  

[Date]2020-01-23
[Paper #]VLD2019-76,CPSY2019-74,RECONF2019-66
Memory access optimization for convolution with scheduling transformations of dependence graphs

Takayuki Todokoro(TCU),  Kenshu Seto(TCU),  

[Date]2020-01-23
[Paper #]VLD2019-69,CPSY2019-67,RECONF2019-59
Full Hardware Synthesis of FreeRTOS-Based Systems

Wakako Nakano(Kwansei Gakuin Univ.),  Nagisa Ishiura(Kwansei Gakuin Univ.),  Hiroyuki Tomiyama(Ritsumeikan Univ.),  Hiroyuki Kanbara(ASTEM),  

[Date]2020-01-23
[Paper #]VLD2019-70,CPSY2019-68,RECONF2019-60
Binary Synthesis from RISC-V Executables

Shoki Hamana(Kwansei Gakuin Univ.),  Nagisa Ishiura(Kwansei Gakuin Univ.),  

[Date]2020-01-23
[Paper #]VLD2019-71,CPSY2019-69,RECONF2019-61
動画認識フロントエンドを想定した特徴抽出専用ハードウェアの構想

,  

[Date]2020-01-23
[Paper #]VLD2019-77,CPSY2019-75,RECONF2019-67
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