| Presentation | 2020-01-22 DDR4 SDRAM controller for real-time processing So Haramura, Nobuyuki Yamasaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, larger scale programs are frequently used in embedded systems, and a higher capacity of main memory is required. Besides, current semiconductor manufacturing technology has realized DRAM power savings, lower prices, and higher capacities. Therefore, high capacity DRAM is widely used as main memory in embedded devices. However, the gap between memory and processor speed is increasing, there is the memory wall problem that the access latency to the memory increases. The worst case execution time of the task will increase, and the time predictability of the task decreases. Furthermore, if time predictability decreases, high grained task execution should be impossible. In this paper, we proposed a prioritized real-time DDR4 SDRAM controller to improve the high priority tasks performance. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DDR4 / real-time / DRAM controller |
| Paper # | VLD2019-56,CPSY2019-54,RECONF2019-46 |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | IPSJ-SLDM / RECONF / VLD / CPSY / IPSJ-ARC |
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| Conference Date | 2020/1/22(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Yutaka Tamiya(Fujitsu Lab.) / Yuichiro Shibata(Nagasaki Univ.) / Nozomu Togawa(Waseda Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Daisuke Fukuda(Fujitsu Labs.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) |
| Secretary | (Univ. Shiga Prefecture) / Kentaro Sano(NTT) / Yoshiki Yamaguchi(Mitsubishi Electric) / Daisuke Fukuda(Hiroshima City Univ.) / Michihiro Koibuchi(e-trees.Japan) / Kota Nakajima(Univ. of Aizu) / (Hitachi) |
| Assistant | / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Kazuki Ikeda(Hitachi) / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) |
| Paper Information | |
| Registration To | Special Interest Group on System and LSI Design Methodology / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | DDR4 SDRAM controller for real-time processing |
| Sub Title (in English) | |
| Keyword(1) | DDR4 |
| Keyword(2) | real-time |
| Keyword(3) | DRAM controller |
| 1st Author's Name | So Haramura |
| 1st Author's Affiliation | Keio University(Keio Univ.) |
| 2nd Author's Name | Nobuyuki Yamasaki |
| 2nd Author's Affiliation | Keio University(Keio Univ.) |
| Date | 2020-01-22 |
| Paper # | VLD2019-56,CPSY2019-54,RECONF2019-46 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-371,CPSY-372,RECONF-373 |
| Page | pp.pp.13-17(VLD), pp.13-17(CPSY), pp.13-17(RECONF), |
| #Pages | 5 |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) |