Engineering Sciences/NOLTA-Reliability(Date:2007/05/10)

Presentation
表紙

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[Date]2007/5/10
[Paper #]
目次

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[Date]2007/5/10
[Paper #]
正誤表

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[Date]2007/5/10
[Paper #]
Query-Transaction Acceleration Appliance with a DRP using Stateful Packet-by-Packet Self-Reconfiguration

Takashi ISOBE,  

[Date]2007/5/10
[Paper #]RECONF2007-1
An Implementation of template matching algorithm using levenshtein distance on FPGA

Souichi SHIMIZU,  Takamasa KANAMORI,  Yoshiaki AJIOKA,  Masatoshi ARAI,  Daisuke KONNO,  Tomomichi NANBA,  Hideharu AMANO,  

[Date]2007/5/10
[Paper #]RECONF2007-2
Automatic combining of rate law functions for an FPGA-based biochemical simulator ReCSiP

Hideki YAMADA,  Naoki IWANAGA,  Yuichiro SHIBATA,  Yasunori OSANA,  Masato YOSHIMI,  Yow IWAOKA,  Yuri NISHIKAWA,  Toshinori KOJIMA,  Hideharu AMANO,  Akira FUNAHASHI,  Noriko HIROI,  Hiroaki KITANO,  Kiyoshi OGURI,  

[Date]2007/5/10
[Paper #]RECONF2007-3
Implementation Experiments of Ocean Model Simulation Using a Reconfigurable Machine SRC-6

Sayaka SHIDA,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2007/5/10
[Paper #]RECONF2007-4
3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication MuCCRA-Cube

Shotaro SAITO,  Yohei HASEGAWA,  Yoshinori KOHAMA,  Yasufumi SUGIMORI,  Hideharu AMANO,  

[Date]2007/5/10
[Paper #]RECONF2007-5
A Hierarchical Context Switching for Dynamically Reconfigurable Hardware

Masaharu YONEDA,  Masaru FUKUSHI,  Susumu HORIGUCHI,  

[Date]2007/5/10
[Paper #]RECONF2007-6
Performance Evaluation of Variable Grain Logic Cell for Arithmetic Circuits

Yoshiaki SATOU,  Motoki AMAGASAKI,  Ryoichi YAMAGUCHI,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2007/5/10
[Paper #]RECONF2007-7
Detailed Evaluation of Delay for the Small-World Network Routing Structure

Yuzo NISHIOKA,  Hisashi TSUKIASHI,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2007/5/10
[Paper #]RECONF2007-8
A Discussion on a Router for embedded Programmable Logic matriX (ePLX)

Naoki OKUNO,  Tomonori IZUMI,  Takeshi FUJINO,  Takenobu IWAO,  Hirofumi NAKANO,  Yoshihiro OKUNO,  Kazutami ARIMOTO,  

[Date]2007/5/10
[Paper #]RECONF2007-9
Techniques to decrease the Configuration Data Transfer Time in Dynamically Reconfigurable Processor MuCCRA

Toru SANO,  Takuro NAKAMURA,  Satoshi TSUTSUMI,  Yohei HASEGAWA,  Hideharu AMANO,  

[Date]2007/5/10
[Paper #]RECONF2007-19
Power Reduction of Dynamical Reconfigurable Processor MuCCRA

Keiichiro HIRAI,  Seidai TAKEDA,  Takashi NISHIMURA,  Yohei HASEGAWA,  Satoshi TSUTSUMI,  Kimiyoshi USAMI,  Hideharu AMANO,  

[Date]2007/5/10
[Paper #]RECONF2007-11
MuCCRA-D : A Dynamically Reconfigurable Processor with Directly Interconnected PEs

Masaru KATO,  Yohei HASEGAWA,  Hideharu AMANO,  

[Date]2007/5/10
[Paper #]RECONF2007-12
A Study of the Dynamic Reconfigurable Processor Vulcan2 and Its Development Tool ISAcc

Tetsuo HIRAKI,  Shingo KADOUCHI,  Yosuke YAMAZAKI,  Takayuki KANDO,  Lovic GAUTHIER,  GOULART FERREIRA Victor MAURO,  Antoine TROUVE,  Koji INOUE,  Kazuaki MURAKAMI,  

[Date]2007/5/10
[Paper #]RECONF2007-13
A Proposal of the Reconfigurable Processing Element for High-speed Parallel Image Processing

Hiroshi KADOTA,  Akiyoshi WAKATANI,  

[Date]2007/5/10
[Paper #]RECONF2007-14
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[Date]2007/5/10
[Paper #]
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[Date]2007/5/10
[Paper #]