Electronics-Silicon Devices and Materials(Date:2004/01/09)

Presentation
表紙

,  

[Date]2004/1/9
[Paper #]
目次

,  

[Date]2004/1/9
[Paper #]
最近のIEDM CMOSセッションにおける地域別研究動向(<特集>IEDM特集:先端CMOSデバイス・プロセス技術)

,  

[Date]2004/1/9
[Paper #]SDM2003-196
Wide-range V_
動作に適した65nm CMOS技術(<特集>IEDM特集:先端CMOSデバイス・プロセス技術)

,  

[Date]2004/1/9
[Paper #]SDM2003-197
65nmノード用高性能25nm CMOS技術(<特集>IEDM特集:先端CMOSデバイス・プロセス技術)

,  

[Date]2004/1/9
[Paper #]SDM2003-198
65nm-node CMOS Process with Ultra-Shallow Junction for Low-Operation-Power Applications (Invited)

Fumio OOTSUKA,  Hiroji OZAKI,  Takaoki SASAKI,  Naoki IZUMI,  Yoshikazu NAKAGAWA,  Akira MINEJI,  Mitsuo YASUHIRA,  Tsunetoshi ARIKADO,  

[Date]2004/1/9
[Paper #]SDM2003-199
Channel Structure Design, Fabrication and Carrier Transport Properties of Strained-Si/SiGe-On-Insulator (Strained-SOI) MOSFETs

Shinichi Takagi,  Tomohisa Mizuno,  Tsutomu Tezuka,  Naoharu Sugiyama,  Toshinori Numata,  Koji Usuda,  Shu Nakaharai,  Yoshihiko Moriyama,  Junji Koga,  Akihito Tanabe,  Norio Hirashita,  Tatsuro Maeda,  

[Date]2004/1/9
[Paper #]SDM2003-200
Scalability of Strained Silicon CMOSFET and High Drive Current Enhancement in the 40nm Gate Length Technology

T. Sanuki,  A. Oishi,  Y. Morimasa,  S. Aota,  T. Kinoshita,  R. Hasumi,  Y. Takegawa,  K. Isobe,  H. Yoshimura,  M. Iwai,  K. Sunouchi,  T. Noguchi,  

[Date]2004/1/9
[Paper #]SDM2003-201
Poly-Si/HfSiO/SiO_2ゲート構造を用いた低電力、高速HfSiOゲートCMOSFET(<特集>IEDM特集:先端CMOSデバイス・プロセス技術)

,  

[Date]2004/1/9
[Paper #]SDM2003-202
Nitrogen Profile Control by Plasma Nitridation Technique for Poly-Si Gate HfSiON CMOSFET with Excellent Interface Property and Ultra-low Leakage Current

Katsuyuki SEKINE,  Seiji INUMIYA,  Motoyuki SATO,  Akio KANEKO,  Kazuhiro EGUCHI,  Yoshitaka TSUNASHIMA,  

[Date]2004/1/9
[Paper #]SDM2003-203
Impace of Actively Body-bias Controlled (ABC) SOI SRAM for Low-Voltage and High-Speed Operation

Takashi IPPOSHI,  Yuuichi HIRANO,  Kouji NII,  Yasumasa TSUKAMOTO,  Shigeto MAEGAWA,  Masahide INUISHI,  Yuzuru OHJI,  

[Date]2004/1/9
[Paper #]SDM2003-204
Low Noise Balanced-CMOS Technology Formed on Si(110) Surface

Akinobu TERAMOTO,  Tatsufumi HAMADA,  Hiroshi AKAHORI,  Keiichi NII,  Koji KOTANI,  Tadahiro OHMI,  

[Date]2004/1/9
[Paper #]SDM2003-205
Unified Mobility Model for High-k Gate Stacks

Shin-ichi SAITO,  Digh HISAMOTO,  Shin'ichiro KIMURA,  Masahiko HIRATANI,  

[Date]2004/1/9
[Paper #]SDM2003-206
複写される方へ

,  

[Date]2004/1/9
[Paper #]
奥付

,  

[Date]2004/1/9
[Paper #]