Electronics-Silicon Devices and Materials(Date:1995/07/27)

Presentation
表紙

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[Date]1995/7/27
[Paper #]
目次

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[Date]1995/7/27
[Paper #]
High-Data-Rate Circuit Technologies for Gigabit-Scale DRAM's

Takeshi Sakata,  Masashi Horiguchi,  Tomonori Sekiguchi,  Hitoshi Tanaka,  Yoshinobu Nakagome,  Masakazu Aoki,  Tohru Kaga,  Makoto Ohkura,  

[Date]1995/7/27
[Paper #]
A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SrTiO_3 and RIE patterned RuO_2/TiN storage node

Shintaro Yamamichi,  Pierre-Yves Lesaicherre,  

[Date]1995/7/27
[Paper #]
New Memory Array Design Technique with Shared Sense And Restore Line

Jae-Kwang Sim,  Jun-Hyun Chun,  Dong-Jun Yang,  Dal-Soo Kim,  

[Date]1995/7/27
[Paper #]
Silane Gas Interactions with Various Silicon Surface

Tsutomu Kojima,  Masakazu Nakamura,  Yasuyuki Shirai,  Masaki Narazaki,  Tadahiro Ohmi,  

[Date]1995/7/27
[Paper #]
Influence of the Shape of the Illumination Aperture on the Intrafield Image Displacement

Byeong-Chan Kim,  Young-Jin Song,  Hong-Seok Kim,  Jeong Jae Kim,  Woo-Shik Kim,  

[Date]1995/7/27
[Paper #]
Limitation for contact hole windows in an attenuated phase shift mask with i-line lithography

Ik-Boum Hur,  Chang-Nam Ahn,  Ki-Ho Baik,  

[Date]1995/7/27
[Paper #]
Fabrication and Characteristics of a Room Temperature 0.05μm-CMOS : Possibility and Design Concept of Sub-0.1μm MOS Devices

Atsushi Hori,  Hiroaki Nakaoka,  Hiroyuki Umimoto,  Michihiko Takase,  Bunji Mizuno,  Shinji Odanaka,  

[Date]1995/7/27
[Paper #]
0.15μm CMOS Process for High Performance and High Reliability

Satoshi Shimizu,  Takashi Kuroi,  Maiko Sakai,  Takeshi Fujino,  Hiroshi Maeda,  Toshiaki Tsutsumi,  Yukinori Hirose,  Shigeru Kusunoki,  Masahide Inuishi,  Tadashi Hirao,  

[Date]1995/7/27
[Paper #]
Fabrication of Dual Gate Transistor with Novel In-Situ Boron-Doped LPCVD Method

J. Moon,  B.H. Kim,  T.E. Shim,  

[Date]1995/7/27
[Paper #]
W/TiN Stacked Gate for ULSI Devices

Mahn-Ho Cho,  Kye-Hee Yeom,  Duck-Hyung Lee,  Jong-Moon J,  Tae-Earn Shim,  

[Date]1995/7/27
[Paper #]
Inversion Layer Mobility of Subhalf-micron MOS Transistors

Duheon Song,  Jongsung Park,  Kyungho Lee,  

[Date]1995/7/27
[Paper #]
A 500MHz 1-stage 32-bit ALU with self-running test circuit : Optimization of pass transistor multiplexers

T. Yoshida,  G. Matsubara,  S. Yoshioka,  H. Tago,  S. Suzuki,  N. Goto,  

[Date]1995/7/27
[Paper #]
A 500-MHz, 0.4-μm CMOS, 32-Word by 32-Bit 3-Port Register File

Masahiro Nomura,  Masakazu Yamashina,  Kazumasa Suzuki,  Masanori Izumikawa,  Hiroyuki Igura,  Hitoshi Abiko,  Kazuhiro Okabe,  Atsuki Ono,  Takashi Nakayama,  Hachiro Yamada,  

[Date]1995/7/27
[Paper #]
A 0.18μm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO

Masayuki Mizuno,  Koichiro Furuta,  Takeshi Andoh,  Akira Tanabe,  Takao Tamura,  Hidenobu Miyamoto,  Akio Furukawa,  Masakazu Yamashina,  

[Date]1995/7/27
[Paper #]
Efficient Multiport Static RAM Design

Jun-Woo Kang,  

[Date]1995/7/27
[Paper #]
Highly Reliable Polysilicon Thin Film Transistor Technology for High Density SRAM Application

Yon Jong Lee,  Jin Ho Choi,  Gug Seon Choi,  Ji Sung Kang,  Hee Koo Yoon,  

[Date]1995/7/27
[Paper #]
[OTHERS]

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[Date]1995/7/27
[Paper #]