Electronics-Integrated Circuits and Devices(Date:2014/01/21)

Presentation
表紙

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[Date]2014/1/21
[Paper #]
目次

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[Date]2014/1/21
[Paper #]
Adaptive Performance Compensation with On-Chip Variation Monitoring

Masanori HASHIMOTO,  

[Date]2014/1/21
[Paper #]ICD2013-100
Analog Mixed-Signal Circuit Techniques for Micro/Nano Sensor Devices

Ippei AKITA,  

[Date]2014/1/21
[Paper #]ICD2013-101
Time Domain Offset Voltage Detector for Self Calibrating Dynamic Latched Comparator

Takayuki OKAZAWA,  Ippei AKITA,  Makoto ISHIDA,  

[Date]2014/1/21
[Paper #]ICD2013-102
A High-efficiency Power Supply Circuit for an RF Energy Harvesting

Shochi ASAI,  Ippei AKITA,  Makoto ISHIDA,  

[Date]2014/1/21
[Paper #]ICD2013-103
A Small On-Chip Antenna for Implantable Devices

Kenji OKABE,  Ippei AKITA,  Makoto ISHIDA,  

[Date]2014/1/21
[Paper #]ICD2013-104
An ultra-low-voltage power-supply monitor circuit for wireless-powered microparticle manipulation system

Ji CUI,  Hirosuke IWASAKI,  Yoshiaki DEI,  Toshimasa MATSUOKA,  

[Date]2014/1/21
[Paper #]ICD2013-105
An Optimum Asymmetric Coding in Each Number of PE cycle for 1Xnm NAND Flash Memories

Senju YAMAZAKI,  Shuhei TANAKAMARU,  Ken TAKEUCHI,  

[Date]2014/1/21
[Paper #]ICD2013-106
Design of a Triple-band GPS CMOS Receiver RF Front-end

Ikkyun Jo,  Jungnam Bae,  Toshimasa Matsuoka,  Takuji Ebinuma,  

[Date]2014/1/21
[Paper #]ICD2013-107
Error-Prediction LDPC for NAND Flash Memory

Tsukasa TOKUTOMI,  Shuhei TANAKAMARU,  Ken TAKEUCHI,  

[Date]2014/1/21
[Paper #]ICD2013-108
FPGA-based Design for Motion-Vector Estimation exploiting High-Speed imaging and its Application to Machine Learning

Masafumi MORI,  Toshiyuki ITOU,  Masayuki IKEBE,  Tetsuya ASAI,  Tadahiro KURODA,  Masato MOTOMURA,  

[Date]2014/1/21
[Paper #]ICD2013-109
STT-MRAM Architecture for Improving Throughput

Haruki Mori,  Koji Yanagida,  Yohei Umeki,  Shusuke Yoshimoto,  Shintaro Izumi,  Masahiko Yoshimoto,  Hiroshi Kawaguchi,  Koji Tsunoda,  Toshihiro Sugii,  

[Date]2014/1/21
[Paper #]ICD2013-110
Phase compensation technique for low-noise small-area three-stage opamp

Hicham HAIBI,  Ippei AKITA,  Makoto ISHIDA,  

[Date]2014/1/21
[Paper #]ICD2013-111
Design of Low-power Delta-Sigma D/A Converter for Wireless Communication with Digitally Assisted Analog Technique

Kenji OHARA,  Takatsugu KAMATA,  Jun WANG,  Takashi OKADA,  Masayuki YAMAGUCHI,  Toshimasa MATSUOKA,  

[Date]2014/1/21
[Paper #]ICD2013-112
Performance Analysis of the Hybrid SSDs with NAND Flash Memory/Storage Class Memory

Shogo HOSAKA,  Shuhei TANAKAMARU,  Koh JOHGUCHI,  Ken TAKEUCHI,  

[Date]2014/1/21
[Paper #]ICD2013-113
Analyzing Data-Retention Characteristics of ReRAM

Hiroki YAMAZAWA,  Shuhei TANAKAMARU,  Ken TAKEUCHI,  

[Date]2014/1/21
[Paper #]ICD2013-114
High-Speed Ferroelectric 6T4C Shadow SRAM for Normally-Off Computing

Tomoki NAKAGAWA,  Shusuke YOSHIMOTO,  Yuki KITAHARA,  Koji YANAGIDA,  Shintaro IZUMI,  Hiroshi KAWAGUCHI,  Masahiko YOSHIMOTO,  

[Date]2014/1/21
[Paper #]ICD2013-115
Low-Power SRAM in 28-nm FD-SOI for Image Processor

Yuta KAWAMOTO,  Shusuke YOSHIMOTO,  Tomomki NAKAGAWA,  Yuki KITAHARA,  Haruki MORI,  Kenta TAKAGI,  Shintaro IZUMI,  Koji NII,  Hiroshi KAWAGUCHI,  Masahiko YOSHIMOTO,  

[Date]2014/1/21
[Paper #]ICD2013-116
Reliability Evaluation of NAND Flash Memories

Yuta KITAMURA,  Shuhei TANAKAMARU,  Ken TAKEUCHI,  

[Date]2014/1/21
[Paper #]ICD2013-117
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