Electronics-Integrated Circuits and Devices(Date:2009/04/06)

Presentation
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[Date]2009/4/6
[Paper #]
目次

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[Date]2009/4/6
[Paper #]
A 1.6GB/s DDR2 128Mb Chain FeRAM_[○!R] with Scalable Octal Bitline and Sensing Schemes

Hidehiro SHIGA,  Daisaburo TAKASHIMA,  Shin-ichiro SHIRATAKE,  Katsuhiko HOYA,  Tadashi MIYAKAWA,  Ryu OGIWARA,  Ryo FUKUDA,  Ryosuke TAKIZAWA,  Kosuke HATSUDA,  Fumiyoshi MATSUOKA,  Yasushi NAGADOMI,  Daisuke HASHIMOTO,  Hisaaki NISHIMURA,  Takeshi HIOKA,  Sumiko DOHMAE,  

[Date]2009/4/6
[Paper #]ICD2009-1
Trend in Multi-Gigabit DRAM Technology and Low-V_t Small-Offset Gated Preamplifier for Sub-1-V Gigabit Arrays

Satoru AKIYAMA,  Tomonori SEKIGUCHI,  Riichiro TAKEMURA,  Akira KOTABE,  Kiyoo ITOH,  

[Date]2009/4/6
[Paper #]ICD2009-2
MRAM technology trend and evolution, 32Mb MRAM development

Tadahiko SUGIBAYASHI,  Ryusuke NEBASHI,  Noboru SAKIMURA,  Hiroaki HONJO,  Shinsaku SAITO,  Yuichi ITO,  Sadahiko MIURA,  Yuko KATO,  Kaoru MORI,  Yasuaki OZAKI,  Yosuke KOBAYASHI,  Norikazu OSHIMA,  Keizo KINOSHITA,  Tetsuhiro SUZUKI,  Kiyokazu NAGAHARA,  Nobuyuki ISHIWATA,  Katsumi SUEMITSU,  Shunsuke FUKAMI,  Hiromitsu HADA,  Naoki KASAI,  

[Date]2009/4/6
[Paper #]ICD2009-3
Which memory technology will win the low-voltage race in SoC?

Hideto HIDAKA,  Masanao YAMAOKA,  Shinji MIYANO,  Satoru AKIYAMA,  Tadahiko SUGIBAYASHI,  Shoichiro KAWASHIMA,  Masataka OSAKA,  

[Date]2009/4/6
[Paper #]ICD2009-4
A Process-Variation-Tolerant Dual-Power-Supply SRAM with 0.179μm^2 Cell in 40nm CMOS Using Level-Programmable Wordline Driver

Yuki FUJIMURA,  Osamu HIRABAYASHI,  Atsushi KAWASUMI,  Azuma SUZUKI,  Yasuhisa TAKEYAMA,  Keiichi KUSHIDA,  Takahiko SASAKI,  Akira KATAYAMA,  Gou FUKANO,  Takaaki NAKAZATO,  Yasushi SHIZUKI,  Natsuki KUSHIYAMA,  Tomoaki YABE,  

[Date]2009/4/6
[Paper #]ICD2009-5
A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme

Shusuke Yoshimoto,  Yusuke Iguchi,  Shunsuke Okumura,  Hidehiro Fujiwara,  Hiroki Noguchi,  Koji Nii,  Hiroshi Kawaguchi,  Masahiko Yoshimoto,  

[Date]2009/4/6
[Paper #]ICD2009-6
A 7T/14T Dependable SRAM and Its Array Structure to Avoid Half Selection

Shunsuke OKUMURA,  Hidehiro FUJIWARA,  Yusuke IGUCHI,  Hiroki NOGUCHI,  Hiroshi KAWAGUCHI,  Masahiko YOSHIMOTO,  

[Date]2009/4/6
[Paper #]ICD2009-7
A 113mm2 32Gb 3bit/Cell NAND Flash Memory and Recent Technology Trend of NAND Flash Memory : The Format of Technical Report (Subtitle)

Takuya Futatsuyama,  Norihiro Fujita,  Naoya Tokiwa,  Yoshihiko Shindo,  Toshiaki Edahiro,  Teruhiko Kamei,  Hiroaki Nasu,  Makoto Iwai,  Koji Kato,  Yasuyuki Fukuda,  Naoaki Kanagawa,  Naofumi Abiko,  Masahide Matsumoto,  Toshihiko Himeno,  Toshifumi Hashimoto,  Yie-Ching Liu,  Hardwell Chivongodze,  Manabu Sakai,  Hong Ding,  Yoshiaki Takeuchi,  Norifumi Kajimura,  Yasuyuki Kajitani,  Kiyofumi Sakurai,  Kosuke Yanagidaira,  Toshihiro Suzuki,  Yuko Namiki,  Tomofumi Fujimura,  Tooru Maruyama,  Toshiharu Watanabe,  Takahiko Hara,  Shigeo Ohshima,  

[Date]2009/4/6
[Paper #]ICD2009-8
A 7.8MB/s 64Gb 4bit/Cell NAND Flash Memory in43nm CMOS

M. Honma,  Cuong Trinh,  N. Shibata,  T. Nakano,  M. Ogawa,  J. Sato,  Y. Takeyama,  K. Isobe,  Binh Le,  Farookh Moogat,  Nima Mokhlesi,  Kenji Kozakai,  Patrick Hong,  Teruhiko Kamei,  K. Iwasa,  J. Nakai,  T. Shimizu,  S. Sakai,  T. Kawaai,  S. Hoshi,  Jonghak Yuh,  Cynthia Hsu,  Taiyuan Tseng,  Jason Li,  Jayson Hu,  Martin Liu,  Shahzad Khalid,  Jiaqi Chen,  Hungszu Lin,  Jeff Yang,  Keith McKay,  Khanh Nguyen,  Trung Pham,  Y. Matsuda,  K. Nakamura,  K. Kanebako,  S. Yoshikawa,  W. Igarashi,  A. Inoue,  T. Takahashi,  Y. Komatsu,  C. Suzuki,  K. Kanazawa,  Masaaki Higashitani,  Sam Lee,  Takashi Murai,  Ken Nguyen,  James Lan,  Sharon Huynh,  Mark Murin,  Mark Shlick,  Menahem Lasser,  Raul Cernea,  Mehrdad Mofidi,  Klaus Schuegraf,  Khandker Quader,  

[Date]2009/4/6
[Paper #]ICD2009-9
A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator for 3D-Integrated NAND Flash SSD

Tadashi YASUFUKU,  Koichi ISHIDA,  Shinji MIYAMOTO,  Hiroto NAKAI,  Makoto TAKAMIYA,  Takayasu SAKURAI,  Ken TAKEUCHI,  

[Date]2009/4/6
[Paper #]ICD2009-10
Reading method of NAND type 1-transistor FeRAM with pulse input

Koichi Sugano,  Shigeyoshi Watanabe,  

[Date]2009/4/6
[Paper #]ICD2009-11
Study for Design Technology of stacked NAND type MRAM using spin transistor

Shoto TAMAI,  Shigeyoshi WATANABE,  

[Date]2009/4/6
[Paper #]ICD2009-12
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[Date]2009/4/6
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[Date]2009/4/6
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[Date]2009/4/6
[Paper #]