Presentation 2009-04-14
A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme
Shusuke Yoshimoto, Yusuke Iguchi, Shunsuke Okumura, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is reduced by 25%, and the cell current is increased by 21%, compared with the prior 10T cell. The minimum operating voltage is lowered by the column line assist (CLA) scheme that suppresses write margin degradation. By measurement, we confirmed that the proposed 128-kb SRAM works at 0.56V.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SRAM / low-voltage operation
Paper # ICD2009-6
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Committee ICD
Conference Date 2009/4/6(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme
Sub Title (in English)
Keyword(1) SRAM
Keyword(2) low-voltage operation
1st Author's Name Shusuke Yoshimoto
1st Author's Affiliation Kobe University()
2nd Author's Name Yusuke Iguchi
2nd Author's Affiliation Kobe University
3rd Author's Name Shunsuke Okumura
3rd Author's Affiliation Kobe University
4th Author's Name Hidehiro Fujiwara
4th Author's Affiliation Kobe University
5th Author's Name Hiroki Noguchi
5th Author's Affiliation Kobe University
6th Author's Name Koji Nii
6th Author's Affiliation Renesas Technology
7th Author's Name Hiroshi Kawaguchi
7th Author's Affiliation Kobe University
8th Author's Name Masahiko Yoshimoto
8th Author's Affiliation Kobe University
Date 2009-04-14
Paper # ICD2009-6
Volume (vol) vol.109
Number (no) 2
Page pp.pp.-
#Pages 6
Date of Issue