Electronics-Integrated Circuits and Devices(Date:2007/12/06)

Presentation
表紙

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[Date]2007/12/6
[Paper #]
目次

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[Date]2007/12/6
[Paper #]
An LSI Design of Frame Rate Conversion Technology for LCD-TV

Akihisa YAMADA,  

[Date]2007/12/6
[Paper #]ICD2007-120
A Current-Mode Transceiver at 625Mb/s, 3mW in 1.5V for Mobile Applications

Tetsuhiro OGINO,  Takefumi YOSHIKAWA,  Makoto NAGATA,  

[Date]2007/12/6
[Paper #]ICD2007-121
A 1.8mm2, 11mA, 23.2dB-NF, discrete-time filter for GSM/WCDMA/WLAN using retiming technique

Tomohiro Sano,  Takaya MARUYAMA,  Ikuo YASUI,  Hisayasu SATO,  Toshihiko SHIMIZU,  

[Date]2007/12/6
[Paper #]ICD2007-122
A 2.4GHz ISM-band digital CMOS wireless transceiver with an intra-symbol adaptively intermittent Rx.

Haruya ISHIZAKI,  Koichi NOSE,  Masayuki MIZUNO,  

[Date]2007/12/6
[Paper #]ICD2007-123
Wide Lock-Range, Low Phase-Noise PLL using Interpolative Ring-VCO with Coarse Frequency Tuning and Frequency Linearization

Hiroshi Kodama,  Hiroyuki Okada,  Kiyoshi Yanagisawa,  Hiromu Ishikawa,  Akio Tanaka,  

[Date]2007/12/6
[Paper #]ICD2007-124
Low jitter and Large-EMI-reduction Spread-spectrum Clock Generator with Auto-calibration for Serial-ATA Application

Takashi KAWAMOTO,  Takayuki NOTO,  Yoshimitsu INADA,  Tomoaki TAKAHASHI,  

[Date]2007/12/6
[Paper #]ICD2007-125
A new SRAM memory cell with small cell ratio using dynamic stability

Yuji KIHARA,  Yutaka ARITA,  Leona OKAMURA,  Hirotoshi SATO,  Tsutomu YOSHIHARA,  

[Date]2007/12/6
[Paper #]ICD2007-126
A Low Dynamic Power and Low Leakage Power 90-nm CMOS SRAM with Wide Operating Margin

Takeshi Iwanari,  Nobuaki Kobayashi,  Tadayoshi Enomoto,  

[Date]2007/12/6
[Paper #]ICD2007-127
A Power-Efficient SRAM Core Architecture with Segmentation-Free and Rectangular Accessibility for Super-Parallel Video Processing

Yuichiro MURACHI,  Junichi MIYAKOSHI,  Tetsuya KAMINO,  Hiroshi KAWAGUCHI,  Masahiko YOSHIMOTO,  

[Date]2007/12/6
[Paper #]ICD2007-128
A Study on Inter-Pipeline Data Transfer Control Circuits for Self-Timed Web-Pipeline

Kazuhiro KOMATSU,  Shuji SANNOMIYA,  Makoto IWATA,  Suguru KAMEDA,  Kazuo TSUBOUCHI,  

[Date]2007/12/6
[Paper #]ICD2007-129
Digital Signal Processing for Motor Driving with Delta-Sigma Modulated ADC

Yasunori KOBORI,  Tetsuya FURUYA,  Yoshihisa YAMADA,  Tomoharu SATO,  Tetsuya TAURA,  Ibuki MORI,  Masashi KONO,  Kazuyuki KOBAYASHI,  Haruo KOBAYASHI,  Yasuhiko KOKAMI,  Hiroshi KUROIWA,  Minoru KUROSAWA,  

[Date]2007/12/6
[Paper #]ICD2007-130
A VGA 30-fps Real-Time Optical-Flow Processor Core for Video Recognition

Hajime ISHIHARA,  Masayuki MIYAMA,  Yuichiro MURACHI,  Hiroshi KAWAGUCHI,  Masahiko YOSHIMOTO,  Yoshio MATSUDA,  

[Date]2007/12/6
[Paper #]ICD2007-131
Four-Pixel accuracy Motion Estimation Unit using Bit-Truncation for Multiple Extended Templates

Tomotaka Katano,  Saburo Johnen,  Takahiro Sasaki,  Kazuhiko Ohno,  Toshio Kondo,  

[Date]2007/12/6
[Paper #]ICD2007-132
Human Extraction Algorithm Using Shape Features and Its VLSI Architecture

Shota HASHIMOTO,  Akio SASAKI,  Masanori HARIYAMA,  Michitaka KAMEYAMA,  

[Date]2007/12/6
[Paper #]ICD2007-133
A Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture

Masanori HARIYAMA,  Shota ISHIHARA,  Michitaka KAMEYAMA,  

[Date]2007/12/6
[Paper #]ICD2007-134
Recent Trend of Transmission Technology for Super High Resolution Images

Sei NAITO,  Shigeyuki SAKAZAWA,  Atsushi KOIKE,  

[Date]2007/12/6
[Paper #]ICD2007-135
A Low Power and High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications

Seiji MOCHIZUKI,  Tetsuya SHIBAYAMA,  Masaru HASE,  Fumitaka IZUHARA,  Kazushi AKIE,  Masaki NOBORI,  Ren IMAOKA,  Hiroshi UEDA,  Kazuyuki ISHIKAWA,  Hiromi WATANABE,  

[Date]2007/12/6
[Paper #]ICD2007-136
Versatile Media Processor for Super High Definition (VMP/SHD) : The scalable architecture of parallel overlay frame engine

Kenji TODA,  Toshihiro KATASHITA,  Yohei HORI,  Osamu MORIKAWA,  

[Date]2007/12/6
[Paper #]ICD2007-137
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