Electronics-Integrated Circuits and Devices(Date:2002/08/16)

Presentation
表紙

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[Date]2002/8/16
[Paper #]
目次

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[Date]2002/8/16
[Paper #]
Design of a Field Programmable VLSI Processor Based on Bit-Serial-Operation Cells

Naotaka OHSAWA,  Masanori HARIYAMA,  Michitaka KAMEYAMA,  

[Date]2002/8/16
[Paper #]ICD2002-64
Endeavor in the Field of Random Sampling : Designing and Prototyping a Processor Suited for its Acceleration

Masa-aki FUKASE,  Takeshi Oyama,  Zhe Liu,  

[Date]2002/8/16
[Paper #]ICD2002-65
A Proposal of a Cell Array Logic-In-Memory VLSI Architecture Specialized in Morphological Operation and its Control Signal Generating Algorithm

Takahiro YONAMINE,  Akio KANOMATA,  Shinya OGASAWARA,  

[Date]2002/8/16
[Paper #]ICD2002-66
A Dual-Rail PLA with 2-Input Logic Cells

Hiroaki YAMAOKA,  Hiroaki YOSHIDA,  Makoto IKEDA,  Kunihiro ASADA,  

[Date]2002/8/16
[Paper #]ICD2002-67
A Method for Reducing Inductive Coupling Noise by Using 3-Phase Data Encoding

Tsuyoshi YAMAMOTO,  Makoto IKEDA,  Kunihiro ASADA,  

[Date]2002/8/16
[Paper #]ICD2002-68
Performance Evaluation on D-Flip-Flop with Manufacturing Fluctuation

Feng LU,  Makoto FURUIE,  BuYeol LEE,  Sadahiro TANI,  Yoshihiro UCHIDA,  Gen FUJITA,  Takao ONOYE,  Shuji TSUKIYAMA,  Shuji NISHI,  Yasushi KUBOTA,  Isao SHIRAKAWA,  Shigeki IMAI,  

[Date]2002/8/16
[Paper #]ICD2002-69
VLSI Implementation of Ogg Vorbis Audio Decoder with Embedded Processor and Specific Hardware

Atsushi KOSAKA,  Satoshi YAMAGUCHI,  HIROYUKI Okuhata,  TAKAO Onoye,  Isao SHIRAKAWA,  

[Date]2002/8/16
[Paper #]ICD2002-70
Substrate Coupling Simulation Suitable for Conventional CAD Tools

Tomohisa KIMURA,  

[Date]2002/8/16
[Paper #]ICD2002-71
Design Rule and its Algorithm for Frequency-Voltage Cooperative Power Control

Kazuo AISAKA,  Toshiyuki ARITSUKA,  Satoshi MISAKA,  Keisuke TOYAMA,  Kunio UCHIYAMA,  Koichiro ISHIBASHI,  Hiroshi KAWAGUCHI,  Takayasu SAKURAI,  

[Date]2002/8/16
[Paper #]ICD2002-72
Memory Circuit technology for High-Speed Low-Power System LSIs

Katsumi Dosaka,  

[Date]2002/8/16
[Paper #]ICD2002-73
0.4-V SRAM Array Using Rectangular-Diffusion Cell and Delta-Boosted-Array-Voltage Scheme

Masanao YAMAOKA,  Kenichi OSADA,  Koichiro ISHIBASHI,  

[Date]2002/8/16
[Paper #]ICD2002-74
90% Write Power Saving SRAM using Sense-Amplifying Memory Cell

Kouichi Kanda,  Takayuki Miyazaki,  Sadaaki Hattori,  Takayasu Sakurai,  

[Date]2002/8/16
[Paper #]ICD2002-75
An Advanced CMOS Technology for Low Power and High Performance LSIs in Sub 100nm CMOS

Hisato Oyamatsu,  

[Date]2002/8/16
[Paper #]ICD2002-76
Importance of high mobility channels on performance of scaled CMOS : High Mobility MOSFETs with Si/SiGe heterostructures

Shin-ichi Takagi,  Tomohisa Mizuno,  Naoharu Sugiyama,  Tsutomu Tezuka,  Toshinori Numata,  Koji Usuda,  Junji Koga,  Yoshihiko Moriyama,  

[Date]2002/8/16
[Paper #]ICD2002-77
A 90 nm CMOS Technology with Ultra-High Speed Transistors, Ultra-High Density SRAM's and Cu/VLK (keff=3.0) Interconnects

Satoshi Nakai,  Development Team CS100,  

[Date]2002/8/16
[Paper #]ICD2002-78
Low Leakage and Low Power Technologies in Sub-100nm Era(Panel Discussion)

Tadayoshi Enomoto,  Akira Matsuzawa,  Makoto Yoshimi,  Masayuki Miyazaki,  Takeshi Sakata,  Hidehiro Takada,  

[Date]2002/8/16
[Paper #]ICD2002-79
[OTHERS]

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[Date]2002/8/16
[Paper #]