| Presentation | 2002/8/16 A 90 nm CMOS Technology with Ultra-High Speed Transistors, Ultra-High Density SRAM's and Cu/VLK (keff=3.0) Interconnects Satoshi Nakai, Development Team CS100, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A 90 nm CMOS technology featuring 40 nm gate length transistors for high end applications, 65 nm gate length for generic, SiC capped Cu/VLK (keff=3.0) interconnects, and 0.999 um2 SRAM's has been developed[1][2]. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 90 nm / transistors / sidewall-notch / interconnects / SiLK / SRAM |
| Paper # | ICD2002-78 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2002/8/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 90 nm CMOS Technology with Ultra-High Speed Transistors, Ultra-High Density SRAM's and Cu/VLK (keff=3.0) Interconnects |
| Sub Title (in English) | |
| Keyword(1) | 90 nm |
| Keyword(2) | transistors |
| Keyword(3) | sidewall-notch |
| Keyword(4) | interconnects |
| Keyword(5) | SiLK |
| Keyword(6) | SRAM |
| 1st Author's Name | Satoshi Nakai |
| 1st Author's Affiliation | Fujitsu Akiruno Technology Center() |
| 2nd Author's Name | Development Team CS100 |
| 2nd Author's Affiliation | Fujitsu Akiruno Technology Center |
| Date | 2002/8/16 |
| Paper # | ICD2002-78 |
| Volume (vol) | vol.102 |
| Number (no) | 274 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |