Electronics-Integrated Circuits and Devices(Date:1997/05/23)

Presentation
表紙

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[Date]1997/5/23
[Paper #]
目次

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[Date]1997/5/23
[Paper #]
Interface Technology of SyncLink DRAM

YOSHINORI OKAJIMA,  

[Date]1997/5/23
[Paper #]ICD97-23
Overview of Kyushu University's Draft Ver. 0.1 for PPRAM-Link Logical Layer

Masaya YAMASAKI,  Koji HASHIMOTO,  Kohichi OKINO,  Kazuaki MURAKAMI,  

[Date]1997/5/23
[Paper #]ICD97-24
Embedded DRAM Technology : DRAM merges to ASIC

Keiichiroh Abe,  Masashi Hashimoto,  

[Date]1997/5/23
[Paper #]ICD97-25
Partial Response Detection Technique for Driver Power Reduction in High-Speed Memory-to-Processor Communications

M. Saito,  Y. Tamura,  K. Gotoh,  S. Wakayama,  J. Ogawa,  Y. Kato,  M. Taguchi,  T. Imamura,  

[Date]1997/5/23
[Paper #]ICD97-26
Improvement of input characteristic using SSTL_3 interface

Takashi ARAKI,  Hisashi IWAMOTO,  Seiji SAWADA,  Masaaki TANIMURA,  Yasumitsu MURAI,  Yasuhiro KONISHI,  Masaki KUMANOYA,  

[Date]1997/5/23
[Paper #]ICD97-27
Power Reduction in Chip Interface using Code-book encoding

Makoto IKEDA,  Kunihiro ASADA,  

[Date]1997/5/23
[Paper #]ICD97-28
Design of Signed Ternary Adder Using LOGO Neural Networks

Shinichi Nakamoto,  Junichi Yamada,  Mititada Morisue,  

[Date]1997/5/23
[Paper #]ICD97-29
Design of Wafer Scale Neuro-Processors Using Redundancy Technology

Nobuhiro Tomabechi,  

[Date]1997/5/23
[Paper #]ICD97-30
[OTHERS]

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[Date]1997/5/23
[Paper #]