| Presentation | 1997/5/23 Embedded DRAM Technology : DRAM merges to ASIC Keiichiroh Abe, Masashi Hashimoto, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An overview of an ASIC process technology logic based embedded DRAM test chip results are reported. This test chip employed 1T1C type cell. 0.5um ASIC process technology is applied. Initial silicon is over 80% yield without changing of process. And this chip has high speed data rate maximum 200MB/S. We confirmed that ASIC module feasibility. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Embedded DRAM / ASIC / Sense Amplifier |
| Paper # | ICD97-25 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/5/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Embedded DRAM Technology : DRAM merges to ASIC |
| Sub Title (in English) | |
| Keyword(1) | Embedded DRAM |
| Keyword(2) | ASIC |
| Keyword(3) | Sense Amplifier |
| 1st Author's Name | Keiichiroh Abe |
| 1st Author's Affiliation | Texas Instruments Japan, Ltd. Miho plant Design Center() |
| 2nd Author's Name | Masashi Hashimoto |
| 2nd Author's Affiliation | Texas Instruments Japan, Ltd. Miho plant Design Center |
| Date | 1997/5/23 |
| Paper # | ICD97-25 |
| Volume (vol) | vol.97 |
| Number (no) | 57 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |