IEICE Technical Committee

Information and Systems-Reconfigurable Systems(Date:2016/01/19)

Presentation

[Fellow Memorial Lecture] Failure May teach Success

Hideharu Aamano(Keio Univ.),

[Date]2016-01-20
[Paper #]VLD2015-90,CPSY2015-122,RECONF2015-72

A Realization of Deep Convolutional Neural Network using the Nested RNS on an FPGA including the Constant Division

Hiroki Nakahara(Ehime Univ.), Tsutomu Sasao(Meiji Univ.), Hisashi Iwamoto(REVSONIC Corp.),

[Date]2016-01-21
[Paper #]VLD2015-108,CPSY2015-140,RECONF2015-90

Implementation of TRAX Solver with Mate Structure

Yasuhiro Takashima(Univ. of Kitakyushu), Takaaki Yahata(Univ. of Kitakyushu), Saki Yamaguchi(Univ. of Kitakyushu), Komei Nomura(Univ. of Kitakyushu),

[Date]2016-01-21
[Paper #]VLD2015-109,CPSY2015-141,RECONF2015-91

Mainframe Assembly to C translation in Legacy Migration

Daisuke Fujiwara(Kwansei Gakuin Univ.), Nagisa Ishiura(Kwansei Gakuin Univ.), Ryo Sakai(Kwansei Gakuin Univ.), Ryo Aoki(SYSTEM'S), Takashi Ogawara(SYSTEM'S),

[Date]2016-01-21
[Paper #]VLD2015-104,CPSY2015-136,RECONF2015-86

Performance Improvement on Music Fingerprint Searching from Large-Scale Database by Using Probabilistic Bias

Masahiro Fukuda(JAIST), Yasushi Inoguchi(JAIST),

[Date]2016-01-21
[Paper #]VLD2015-98,CPSY2015-130,RECONF2015-80

A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations

Koki Igawa(Waseda Univ.), Masao Yanagisawa(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2016-01-21
[Paper #]VLD2015-105,CPSY2015-137,RECONF2015-87

Power Optimization of a Reconfigurable Accelerator by Middle-grained Body Bias Control

Yusuke Matsushita(Keio Univ.), Hayate Okuhara(Keio Univ.), Koichiro Masuyama(Keio Univ.), Yu Fujita(Keio Univ.), Hideharu Amano(Keio Univ.),

[Date]2016-01-21
[Paper #]VLD2015-101,CPSY2015-133,RECONF2015-83

Binary Synthesis Implementing External Interrupt Handler as Independent Module

Naoya Ito(Kwansei Gakuin Univ.), Nagisa Ishiura(Kwansei Gakuin Univ.), Hiroyuki Tomiyama(Ritsumeikan Univ.), Hiroyuki Kanbara(ASTEM),

[Date]2016-01-21
[Paper #]VLD2015-106,CPSY2015-138,RECONF2015-88

Write-Reduction using Encoding data on MLC for Non-Volatile Memories

Masashi Tawada(Waseda Univ.), Shinji Kimura(Waseda Univ.), Masao Yanagisawa(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2016-01-21
[Paper #]VLD2015-107,CPSY2015-139,RECONF2015-89

An Architectural Optimization for Software Defined SSD using Full System Simulator

Shun Gokita(FLL), Satoshi Kazama(FLL), Seiki Shibata(FLL), Shinya Kuwamura(FLL), Eiji Yoshida(FLL), Junji Ogawa(FLL),

[Date]2016-01-21
[Paper #]VLD2015-103,CPSY2015-135,RECONF2015-85

Search of Evaluation Function with Genetic Algorithm and UML Model-based Development for TRAX Player

Ryo Tamaki(Tokai Univ.), Naohiko Shimizu(Tokai Univ.),

[Date]2016-01-21
[Paper #]VLD2015-110,CPSY2015-142,RECONF2015-92

Discussion on FPGA implementation of real-time human detection using FIND features

Yoshiki Hayashida(Nagasaki Univ.), Masahito Oishi(Nagasaki Univ.), Ryo Fujita(Nagasaki Univ.), Yuichiro Shibata(Nagasaki Univ.), Kiyoshi Oguri(Nagasaki Univ.),

[Date]2016-01-21
[Paper #]VLD2015-99,CPSY2015-131,RECONF2015-81

Power Reduction of TLB using Body Bias Control on SOTB

Daiki Kawase(Keio Univ.), Hayate Okuhara(Keio Univ.), Hideharu Amano(Keio Univ.),

[Date]2016-01-21
[Paper #]VLD2015-102,CPSY2015-134,RECONF2015-84

FPGA Implementation of a Peak Detection System using AMPD Algorithm

Fumihiko Iwasaki(Nagasaki Univ), Yuichiro Shibata(Nagasaki Univ), Kiyoshi Oguri(Nagasaki Univ),

[Date]2016-01-21
[Paper #]VLD2015-100,CPSY2015-132,RECONF2015-82