| Presentation | 2016-01-21 Write-Reduction using Encoding data on MLC for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | There is a movement to use the non-volatile memory to the important main memory in von Neumann computer. Non-volatile memory is a low endurance and costs high writing energy. They are solved to reduce the bit-write amount by encoding. Recently, the practical application requests MLC non-volatile memory increases, the coding technique in the conventional single-level cell occurs discrepancy modeling problems. We propose write-reduction using encoding data on MLC for non-volatile memories. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Non-volatile memory / bit write reduction / Encoding/decoding / MLC |
| Paper # | VLD2015-107,CPSY2015-139,RECONF2015-89 |
| Date of Issue | 2016-01-12 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | VLD / CPSY / RECONF / IPSJ-SLDM / IPSJ-ARC |
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| Conference Date | 2016/1/19(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Masahiro Fukui(Ritsumeikan Univ.) / Masahiro Goshima(国情研) |
| Vice Chair | Takashi Takenana(NEC) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(Fujitsu Labs.) / Masato Motomura(NII) / Yuichiro Shibata(Toshiba) / (Univ. of Tsukuba) / (Sharp) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Special Interest Group on System and LSI Design Methodology / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Write-Reduction using Encoding data on MLC for Non-Volatile Memories |
| Sub Title (in English) | |
| Keyword(1) | Non-volatile memory |
| Keyword(2) | bit write reduction |
| Keyword(3) | Encoding/decoding |
| Keyword(4) | MLC |
| 1st Author's Name | Masashi Tawada |
| 1st Author's Affiliation | Waseda University(Waseda Univ.) |
| 2nd Author's Name | Shinji Kimura |
| 2nd Author's Affiliation | Waseda University(Waseda Univ.) |
| 3rd Author's Name | Masao Yanagisawa |
| 3rd Author's Affiliation | Waseda University(Waseda Univ.) |
| 4th Author's Name | Nozomu Togawa |
| 4th Author's Affiliation | Waseda University(Waseda Univ.) |
| Date | 2016-01-21 |
| Paper # | VLD2015-107,CPSY2015-139,RECONF2015-89 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-398,CPSY-399,RECONF-400 |
| Page | pp.pp.221-225(VLD), pp.221-225(CPSY), pp.221-225(RECONF), |
| #Pages | 5 |
| Date of Issue | 2016-01-12 (VLD, CPSY, RECONF) |