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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SIS | 2023-12-07 11:00 |
Aichi | Sakurayama Campus, Nagoya City University (Primary: On-site, Secondary: Online) |
Data Path Parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware Yuka Otani, Akira Yamawaki (Kyutech)  SIS2023-24 |
A mobile terminal architecture which can dynamically reconfigure the optimal hardware for each application can achieve h... [more] | SIS2023-24 pp.1-6 |
| CPSY, IPSJ-ARC, IPSJ-HPC | 2023-12-05 10:55 |
Okinawa | Okinawa Industry Support Center (Primary: On-site, Secondary: Online) |
Performance improvements of Multi-Platform Parallel Computing System Based on Web Technologies Soki Imaizumi, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) CPSY2023-27 |
Web browsers can be used as architecture-independent execution environments, and nowadays they can provide the same func... [more] | CPSY2023-27 pp.1-6 |
| EE, IEE-HCA | 2023-05-26 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
Development of a High-Efficiency Wireless Power Transfer System for Taiwan's First Autonomous Electric Boat Charging Ching-Ming Lai (NCHU), Tomokazu Mishima (Kobe Univ.) EE2023-2 |
This study presents the system architecture and demonstration of a high-efficiency wireless power transfer (WPT) system ... [more] | EE2023-2 pp.7-11 |
| HWS, VLD [detail] | 2021-03-03 13:00 |
Online | Online | [Memorial Lecture]
Scheduling Sparse Matrix-Vector Multiplication onto Parallel Communication Architecture Mingfei Yu, Ruitao Gao, Masahiro Fujita (Univ. Tokyo) VLD2020-71 HWS2020-46 |
There is an obvious trend to make use of hardware including many-core CPU, GPU and FPGA, to conduct computationally inte... [more] | VLD2020-71 HWS2020-46 pp.24-29 |
| SIP | 2020-08-27 16:00 |
Online | Online | [Invited Talk]
Bringing out Computer Performance on Image Processing Programming Kenjiro Sugimoto (Waseda Univ.) SIP2020-33 |
Along with the complication of computer architecture, more advanced and delicate programming techniques have been requir... [more] | SIP2020-33 p.17 |
| WPT, EE (Joint) |
2018-10-03 11:25 |
Kyoto | Kyoto Univ. Uji Campus | Operation Characteristics of Input-Series-Output-Parallel LLC Resonant DC-DC Converter based on Interleaved Principle and Its Experimental Evaluations Masaki Hanauchi, Tomokazu Mishima (Kobe Univ.) EE2018-19 |
An Input-series-output-parallel (ISOP) switching power converter topology is suitable for electric power processing arch... [more] | EE2018-19 pp.7-10 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch Tetsuaki Fujimoto (Ritsumeikan Univ.), Wataru Takahashi, Kazutoshi Wakabayashi (NEC), Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-38 DC2017-44 |
This report proposes an optimal implementation of FFT circuit for mixed grained reconfigurable architecture using via-sw... [more] | VLD2017-38 DC2017-44 pp.67-72 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-08 12:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | CPSY2017-45 |
Generally, HDL simulation is used for development and verification of processor design. However, the simulation speed i... [more] |
CPSY2017-45 pp.53-58 |
| SDM, ICD, ITE-IST [detail] | 2017-08-02 14:10 |
Hokkaido | Hokkaido-Univ. Multimedia Education Bldg. | A Quadrature-modulation EPWM Transmitter with Parallel-Output MASH Delta-Sigma Modulator Takumi Yamamoto, Yohtaro Umeda (Tokyo Univ. of Science), Yusuke Kozawa (Ibaraki Univ.) SDM2017-48 ICD2017-36 |
In this paper, Multi StAge Noise Shaping (MASH) architecture is employed to realize high noise reduction capability by n... [more] | SDM2017-48 ICD2017-36 pp.123-128 |
| DC | 2016-06-20 15:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Partially Parallel Time Domain Reed Solomon Decoder Kentaro Kato (NIT, Tsuruoka College), Somsak Choomchuay (KMITL) DC2016-15 |
This paper proposes a partially parallel time domain reed solomon decoder to reduce the decoding time. The proposed dec... [more] |
DC2016-15 pp.31-36 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-20 15:05 |
Kanagawa | Hiyoshi Campus, Keio University | A Parallel Algorithm for Realizing the MacCormack Scheme in Computational Fluid Dynamics and its FPGA Implementation Yusuke Haga, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.) VLD2015-93 CPSY2015-125 RECONF2015-75 |
In many partial differential equation models used in various applications such as fluid analysis, their analytical solut... [more] | VLD2015-93 CPSY2015-125 RECONF2015-75 pp.137-142 |
| R | 2015-10-16 11:00 |
Fukuoka | Irregularity Countermeasures in Massively Parallel BigData Processors Marat Zhanikeev (Kyutech) R2015-53 |
The term Massively Parallel BigData Processor names a recent advance in bigdata processing technology which has advanced... [more] | R2015-53 pp.7-14 |
|
| DC, CPSY | 2015-04-17 14:15 |
Tokyo | Parallel Processor Architecture based on Small World Connection Hideki Mori (Meiji Univ.), Minoru Uehara, Katsuyoshi Matsumoto (Toyo Univ.) CPSY2015-10 DC2015-10 |
The technology of circuit refinement has achieved a tremendous large-scale integration, so huge VLSI systems have emerge... [more] | CPSY2015-10 DC2015-10 pp.53-58 |
|
| EID, ITE-IDY, IEIJ-SSL, IEE-EDD, SID-JC [detail] | 2015-01-22 15:08 |
Kyoto | Ryukoku University | Development of high frame rate LED screen by column-parallel processing Kengo Sato, Teppei Kobayashi, Akinori Tsuji, Shiro Suyama (Univ. of Tokushima), Hirotsugu Yamamoto (Utsunomiya Univ.) |
We have developed a high-frame-rate LED screen. Conventional LED display architecture has a latency problem between LED ... [more] | |
| ICD, CPSY | 2014-12-01 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Poster Presentation]
A Study on a Comprehensive Architecture Exploration Environment for Emerging Applications Shohei Takeuchi, Shinya Takamaeda Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST) ICD2014-77 CPSY2014-89 |
Emerging applications, such as graph processing and machine learning, contain several irregular memory access patterns a... [more] | ICD2014-77 CPSY2014-89 pp.25-27 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2014-10-02 14:15 |
Miyagi | Hierarchical GALS system based on ring segmented bus architecture Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.) VLD2014-63 ICD2014-56 IE2014-42 |
A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed as an asynchronous bus a... [more] | VLD2014-63 ICD2014-56 IE2014-42 pp.19-24 |
|
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2014-03-16 14:30 |
Okinawa | A parallelizing compiler cooperative acceleration technique of multicore architecture simulation using a statistical method Gakuho Taguchi, Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2013-117 DC2013-104 |
A parallelizing compiler cooperative acceleration technique for multicore architecture simulation is proposed in this pa... [more] | CPSY2013-117 DC2013-104 pp.289-294 |
|
| SIS | 2014-03-06 11:40 |
Osaka | Gran Front Osaka, Knowledge Capital C-9F, 901 | Hardware Implementation of Soft Cascaded SVM Classifier Kazutaka Takeuchi, Jaehoon Yu (Osaka Univ.), Ryusuke Miyamoto (Meiji Univ.), Takao Onoye (Osaka Univ.) SIS2013-58 |
To speed up the object detection without degradation of the accuracy, the following two approaches are proposed: Reducin... [more] | SIS2013-58 pp.17-22 |
| NS | 2013-04-18 16:25 |
Ishikawa | The Wajima Chamber of Commerce and Industry | A Study of the Data Merging on the Distributed Processing Framework Satoshi Kondoh, Masashi Kaneko, Takeshi Fukumoto (NTT) NS2013-4 |
Recently, to acquire the high reliance and the high performance for the increase of the number of users, we often apply ... [more] | NS2013-4 pp.19-22 |
| COMP | 2012-10-31 16:45 |
Miyagi | Tohoku University | A Novel Computation Model for GPU Atsushi Koike, Kunihiko Sadakane (NII) COMP2012-42 |
We propose a novel computation model for GPU. Known parallel computation models such as the PRAM model are not appropria... [more] | COMP2012-42 pp.53-60 |
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