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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 20  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, VLD 2024-01-29
10:30
Kanagawa AIRBIC Meeting Room 1-4
(Primary: On-site, Secondary: Online)
Random number generation on the Rocket core with a built-in LFSR
Takayoshi Shikano, Shuichi Ichikawa (Toyohashi Tech.) VLD2023-80 RECONF2023-83
Masaoka et al. developed an unpredictable random number generator (URNG) using a built-in linear feedback shift register... [more] VLD2023-80 RECONF2023-83
pp.1-6
DC 2022-03-01
14:45
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
SAT-based LFSR Seed Generation for Delay Fault BIST
Kotaro Iwamoto, Satoshi Ohtake (Oita Univ.) DC2021-74
So far, a one-pass LFSR seed generation method for delay fault BIST has been proposed. The method directly generates see... [more] DC2021-74
pp.57-62
ICD, CPSY, CAS 2017-12-14
15:10
Okinawa Art Hotel Ishigakijima Study on acceleration of Paralleled Linear Feedback Shift Register PRBS Generator
Keisuke Iyama, Masaki Ishii, Masahiro Sasaki (SIT) CAS2017-85 ICD2017-73 CPSY2017-82
The operation speed of the on-chip test pattern generator that tests normal operation of LSI chip is determined by the p... [more] CAS2017-85 ICD2017-73 CPSY2017-82
p.99
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-06
14:30
Kumamoto Kumamoto-Kenminkouryukan Parea A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST
Kyonosuke Watanabe, Satoshi Ohtake (Oita Univ.) VLD2017-35 DC2017-41
With the miniaturization and high speed of large scale integrated circuits, it has become important to test delay faults... [more] VLD2017-35 DC2017-41
pp.49-54
DC 2016-02-17
14:25
Tokyo Kikai-Shinko-Kaikan Bldg. Built-In Self-Test with Combination of Weighted Random Pattern and Reseeding
Sayaka Satonaka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) DC2015-92
Built-In Self-Test (BIST) is widely used to reduce test cost. However, it is difficult to achieve high fault coverage wi... [more] DC2015-92
pp.37-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
14:10
Nagasaki Nagasaki Kinro Fukushi Kaikan An approach to LFSR/MISR seed generation for delay fault BIST
Daichi Shimazu, Satishi Ohtake (Oita Univ.) VLD2015-70 DC2015-66
In this paper, we propose a method of LFSR/MISR seed generation for delay fault BIST.
A widely used conventional way to... [more]
VLD2015-70 DC2015-66
pp.213-218
RECONF 2015-06-20
11:10
Kyoto Kyoto University A Rapid Verification Environment for Statistical Evaluation of PUF Circuits
Toshihiro Katashita, Yasunori Onda, Yohei Hori (AIST) RECONF2015-18
In this study, we constructed a rapid experimentation environment for Physically Unclonable Function (PUF) circuit verif... [more] RECONF2015-18
pp.97-102
ICSS 2015-03-04
09:50
Okinawa Meio Univiersity A study on the safety of the pseudo-random number generator in RFID
Hiroyuki Sato (JAIST), Atsuko Miyaji (JAIST/JST CREST), Chunhua Su (JAIST) ICSS2014-75
One of the ways of verifing that whether pseudo-random number generator (PRNG) meets the security requirements or not is... [more] ICSS2014-75
pp.73-78
DC 2015-02-13
15:20
Tokyo Kikai-Shinko-Kaikan Bldg A Method of LFSR Seed Generation for Hierarchical BIST
Kosuke Sawaki, Satoshi Ohtake (Oita Univ.) DC2014-85
A linear feedback shift register (LFSR) is used as a test pattern generator of built-in self-test (BIST).
In BIST, alth... [more]
DC2014-85
pp.43-48
SIP, CAS, MSS, VLD 2013-07-12
14:10
Kumamoto Kumamoto Univ. On Auto-Correlation Properties of Random Binary Sequences with Post-Processing Based on Chaos Theory
Kota Morikawa, Akio Tsuneda (Kumamoto Univ.) CAS2013-29 VLD2013-39 SIP2013-59 MSS2013-29
In Monte Carlo simulations, not only uncorrelated random sequences but also correlated ones are useful for simulating va... [more] CAS2013-29 VLD2013-39 SIP2013-59 MSS2013-29
pp.159-163
DC 2013-06-21
14:15
Tokyo Kikai-Shinko-Kaikan Bldg. A method of deterministic LFSR seed generation for scan-based BIST
Takanori Moriyasu, Satoshi Ohtake (Oita Univ.) DC2013-11
This paper proposes a method of LFSR seed generation for LFSR reseeding of scan-based BIST of VLSI circuits. So far, a s... [more] DC2013-11
pp.7-12
RECONF 2013-05-21
14:45
Kochi Kochi Prefectural Culture Hall Performance Evaluation of Physical Unclonable FUnctions on Kintex-7 FPGA
Yohei Hori, Toshihiro Katashita, Kazukuni Kobara (AIST) RECONF2013-17
The challenge-response properties of Physical Unclonable Functions (PUFs) on 28-nm process FPGA on the ten
SASEBO-GIII ... [more]
RECONF2013-17
pp.91-96
CAS 2013-01-28
09:25
Oita Beppu International Convention Center Performance Evaluation of Spreading Codes with Negative Auto-Correlation Based on M-sequences and Chaos Theory
Shohei Tokunaga, Akio Tsuneda (Kumamoto Univ.) CAS2012-66
Spreading codes with appropriate negative auto-correlation can reduce average multiple access interference (MAI) in asyn... [more] CAS2012-66
pp.5-10
CAS 2012-01-19
14:45
Fukuoka Kyushu Univ. Evaluation of Spreading Codes with Negative Auto-Correlation Based on M-Sequences and Chaos Theory
Shohei Tokunaga, Akio Tsuneda (Kumamoto Univ.) CAS2011-95
Spreading sequences with appropriate negative auto-correlation can reduce average multiple access interference (MAI) in ... [more] CAS2011-95
pp.59-62
CAS, NLP 2009-01-23
10:00
Miyazaki   BER Performance of Spreading Sequences with Negative Auto-correlations Based on Chaos Theory and LFSR Sequences
Akio Tsuneda, Yasunori Miyazaki (Kumamoto Univ.) CAS2008-87 NLP2008-117
In asynchronous DS/CDMA systems, spreading sequences with appropriate
negative auto-correlation properties can outperfo... [more]
CAS2008-87 NLP2008-117
pp.131-136
NLP 2007-11-22
16:00
Fukuoka   Design and Evaluation of Spreading Sequences with Negative Auto-correlations Based on Chaos Theory and LFSR Sequences
Yasunori Miyazaki, Akio Tsuneda, Takahiro Inoue (Kumamoto Univ.) NLP2007-104
In DS/CDMA systems, spreading sequences play an important role since they dominate the system performance such as bit er... [more] NLP2007-104
pp.51-55
NLP 2007-11-22
16:25
Fukuoka   A Study on Maximal-Period Sequences Generated by Feedback-Switching NFSR
Raphael Eboku, Akio Tsuneda, Takahiro Inoue (Kumamoto Univ.) NLP2007-105
We propose a method to generate sequences using feedback-limited
nonlinear feedback shift registers (NFSRs) with switc... [more]
NLP2007-105
pp.57-60
NLP 2006-05-11
12:30
Kumamoto Kumamoto Univ. A Study on Test Pattern Generation for LSI Tests Using Chaotic Sequences
Atsushi Izukura, Ryusuke Tsuchida, Kunihiko Kudou, Daisaburo Yoshioka, Akio Tsuneda, Takahiro Inoue (Kumamoto Univ.)
Linear feedback shift registers (LFSRs) are extensively used in built-in self-test (BIST) as a test pattern generator (T... [more] NLP2006-1
pp.1-4
IT 2005-09-27
14:45
Fukushima Aizu Univ. A consideration on maximum-likelihood decoding for Reed-Solomon codes
Muneyuki Shotsu (Shinshu Univ.), Masazumi Kurihara (Univ. of Electro-Com.), Tatsuo Sugimura (Shinshu Univ.)
In the report, the efficient method of maximum-likelihood decoding for Reed-Solomon(R-S) code is proposed. The maximum-l... [more] IT2005-54
pp.19-24
ICD, CPM 2005-01-28
15:00
Tokyo Kikai-Shinko-Kaikan Bldg. Selection of Seeds and Phase Shifters for Scan BIST
Masayuki Arai, Harunobu Kurokawa, Kenichi Ichino, Satoshi Fukumoto, Kazuhiko Iwasaki (Tokyo Metro. Univ.)
In this paper, we discuss the application of a seed-selection procedure for LFSR-based BIST to multiple scan chains, com... [more] CPM2004-171 ICD2004-216
pp.53-58
 Results 1 - 20 of 20  /   
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