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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 21 - 40 of 71 [Previous]  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
COMP 2014-09-02
11:30		 Aichi Toyohashi University of Technology On the number of matrix multiplications in the evaluation of the matrix polynomial I+A+A^2+...+A^{N-1}
Kotaro Matsumoto, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) COMP2014-18		  [more] COMP2014-18
pp.23-27
SCE 2014-07-23
10:10		 Tokyo Kikai-Shinko-Kaikan Bldg. Design and Evaluation of the 4-Bit Parallel Bit-Slice-ALU
Kensuke Takata, Masamitsu Tanaka, Akira Fujimaki (Nagoya Univ.), Tang Gaung-Ming, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) SCE2014-25		  [more] SCE2014-25
pp.7-12
DC 2014-06-20
15:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Floating-point Multiplier with Reduced Precision Error Checking by Partial Duplication
Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.) DC2014-15		 We propose a floating-point multiplier with reduced precision error checking.
The multiplier uses a truncated multiplie... [more]		 DC2014-15
pp.33-38
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2013-03-14
15:30		 Nagasaki   Evaluation Environment for Configuration of Floating-Point Unit Arrays
Yuya Itoh, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) CPSY2012-94 DC2012-100		 A floating-point unit array that is constructed by connecting floating-point units, is expected to be an excellent archi... [more] CPSY2012-94 DC2012-100
pp.253-258
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2013-03-14
15:05		 Nagasaki   Self-Checking Carry Look-ahead Adder by Carry-bit Duplication
Akihiro Mitoma (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2012-98 DC2012-104		 We propose a self-checking carry look-ahead adder, which can detect errors caused by a single stuck-at fault in the adde... [more] CPSY2012-98 DC2012-104
pp.277-282
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2013-03-14
15:30		 Nagasaki   Multiplier with concurrent error detection by particial duplication
Kazushi Akimoto (Kyoto Univ.), Nobutaka Kito (Cyukyo Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2012-99 DC2012-105		 We propose a multiplier with concurrent error detection, which can detect the error more than the designated numerical v... [more] CPSY2012-99 DC2012-105
pp.283-287
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-27
10:30		 Fukuoka Centennial Hall Kyushu University School of Medicine A speculative execution method for indefinite loops in high level synthesis
Tatsuma Araki, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ) VLD2012-76 DC2012-42		  [more] VLD2012-76 DC2012-42
pp.99-104
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-28
16:50		 Fukuoka Centennial Hall Kyushu University School of Medicine A Design Method of Fault-Secure Parallel Prefix Adders by Carry-Bit Duplication
Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) VLD2012-106 DC2012-72		 We show a design method of fault-secure parallel prefix adders with various prefix structures.
Adders by the method gen... [more]		 VLD2012-106 DC2012-72
pp.273-278
SCE 2012-07-19
11:10		 Tokyo Kikai-Shinko-Kaikan Bldg. SFQ Bit-Slice Floating Point Adder
Yukio Ohmomo, Yohei Naruse (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) SCE2012-11		 Single Flux Quantum (SFQ) circuits operate at high-speed with low-power consumption.
A Large-Scale Reconfigurable Data ... [more]		 SCE2012-11
pp.13-17
SCE 2012-07-19
11:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Design of a 2bit Bit-Slice Half-Precision Floating-Point Multiplier Using SFQ Circuits
Yohei Naruse (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) SCE2012-12		 Single flux quantum (SFQ) circuits are expected as next-generation circuits.
Arithmetic circuits using SFQ circuits ha... [more]		 SCE2012-12
pp.19-23
VLD 2012-03-06
15:30		 Oita B-con Plaza CDFG Transformation Based on Speculation Exploiting Implicit Parallelism in Behavioral Synthesis
Shinji Ohno (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) VLD2011-129		 In recent years, circuit design in languages with higher abstraction level has been widely noticed to address the proble... [more] VLD2011-129
pp.55-60
VLD 2012-03-07
10:45		 Oita B-con Plaza Equivalence Checking Method of Timed Logic Formulae for Design Verification of Single-Flux Quantum Circuits
Takahiro Kawaguchi (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) VLD2011-135		 This paper proposes an equivalence checking method of timed logic formulae for reducing number of
states in verificatio... [more]		 VLD2011-135
pp.91-96
SCE 2011-10-12
15:40		 Tokyo Kikai-Shinko-Kaikan Bldg. Development of Nb multi-layer Advanced Fabrication Process for Large-scale SFQ Circuits
Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh, Mutsuo Hidaka (ISTEC-SRL), Akira Fujimaki, Hiroyuki Akaike (Nagoya Uni.), Nobuyuki Yoshikawa (Yohohama National Uni.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Uni.) SCE2011-18		 We have been developing a Nb multi-layer fabrication process for large-scale SFQ circuits. We have been evaluating both ... [more] SCE2011-18
pp.37-42
SCE 2011-07-13
15:40		 Tokyo Kikai-Shinko-Kaikan Bldg. High-Throuput Bit-Slice Multipliers Using SFQ Circuits
Yohei Naruse, Nobutaka Kito, Naofumi Takagi (Kyoto Univ.) SCE2011-9		 Single flux quantum (SFQ) circuits are expected as next-generation circuits. Arithmetic circuits using SFQ circuits have... [more] SCE2011-9
pp.47-52
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2011-03-18
10:55		 Okinawa   Modeling of Timing Faults and Test Generation for Single Flux Quantum Logic Circuits
Nobutaka Kito (Kyoto Univ.), Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2010-74 DC2010-73		 Single Flux Quqntum(SFQ) logic circuits are expected to achieve
ultra-high-performance computers with low power.
For r... [more]		 CPSY2010-74 DC2010-73
pp.51-56
VLD 2011-03-04
10:00		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center A Routing Method for Multi-Layer Single Flux Quantum Circuits with Wire Ordering based on Slack Allocation
Shota Takeshima, Kazuyoshi Takagi, Masamitsu Tanaka (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) VLD2010-137		  [more] VLD2010-137
pp.123-128
VLD 2011-03-04
14:00		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Acceleration of Bounded Model Checking for Sequential Circuits with Two-phase Verification
Norihiro Ono, Kazuhiro Nakamura, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) VLD2010-143		  [more] VLD2010-143
pp.159-164
SCE 2010-10-19
15:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Demonstration of a 2x2 Single-Flux-Quantum Reconfigurable Data-Path Based on the 10-kA/cm2 Process
Masakazu Okada, Irina Kataeva, Masato Ito, Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki (Nagoya Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.), Shuuichi Nagasawa (ISTEC), Naofumi Takagi (Kyoto Univ.) SCE2010-33		 We have demonstrated a reconfigurable data-path (RDP) prototype using the single-flux-quantum (SFQ) circuits fabricated ... [more] SCE2010-33
pp.55-60
SCE 2010-07-22
11:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Fault Modeling and Test Generation for Single Flux Quantum Logic Circuits
Nobutaka Kito (Kyoto Univ.), Masamitsu Tanaka, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) SCE2010-19		 This report discusses fault modeling and test generation for
Single Flux Quqntum(SFQ) logic circuits.
SFQ circuits ar... [more]		 SCE2010-19
pp.31-35
SCE 2010-07-22
13:15		 Tokyo Kikai-Shinko-Kaikan Bldg. Investigation to Speed Up Single-flux-quantum Circuits by Applying Higher Bias Voltage
Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki, Kazuyoshi Takagi (Nagoya Univ./JST), Nobuyuki Yoshikawa (Yokohama National Univ./JST), Shuichi Nagasawa (SRL/JST), Naofumi Takagi (Kyoto Univ./JST) SCE2010-20		  [more] SCE2010-20
pp.37-40
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