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Technical Committee on Reconfigurable Systems (RECONF) (Searched in: 2010)
Search Results: Keywords 'from:2011-01-17 to:2011-01-17'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 11:15 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Optimization of Local Routing Networks in a Logic Block for Cluster Based FPGAs Yuji Masumitsu, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)  VLD2010-104 CPSY2010-59 RECONF2010-73 |
Feild programmable gate arrays (FPGAs) are mostly cluseter-based FPGAs. In a cluster-based FPGA, a logic block consists ... [more] | VLD2010-104 CPSY2010-59 RECONF2010-73 pp.139-144 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 11:35 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Test Scheme for Interconnect of FPGA Focused on Switch Block Topology Hiroki Yosho, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2010-105 CPSY2010-60 RECONF2010-74 |
In general, an ATPG(Automatic Test Pattern Generation) is used to test LSI. However, because logic function and wiring r... [more] | VLD2010-105 CPSY2010-60 RECONF2010-74 pp.145-150 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 11:55 |
Kanagawa | Keio Univ (Hiyoshi Campus) | MEMS allowable alignment errors of a MEMS dynamic optically reconfigurable gate array Hironobu Morita, Minoru Watanabe (Shizuoka Univ.) VLD2010-106 CPSY2010-61 RECONF2010-75 |
[more] | VLD2010-106 CPSY2010-61 RECONF2010-75 pp.151-156 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 13:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | [Invited Talk]
Design of Asynchronous Circuits with Bundled-data Implementation on FPGA Hiroshi Saito (Univ. Aizu) VLD2010-107 CPSY2010-62 RECONF2010-76 |
This report initially introduces several researches related to asynchronous circuits and FPGAs. Then, this report propos... [more] | VLD2010-107 CPSY2010-62 RECONF2010-76 pp.157-162 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 14:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator Shuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (Aizu Univ.) VLD2010-108 CPSY2010-63 RECONF2010-77 |
Recently, System on a Chip (SoC) has problems increasing of the scale of circuit and design cost, because SoC contains m... [more] | VLD2010-108 CPSY2010-63 RECONF2010-77 pp.163-168 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 14:50 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Silent Large Datapath : A Ultra Low Power Accelarater Yoshihiro Yasuda, Nobuaki Ozaki, Masayuki Kimura, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-109 CPSY2010-64 RECONF2010-78 |
Silent Large Datapath (SLD) is a low power reconfigurable accelerator for high performance embedded systems. By using a... [more] |
VLD2010-109 CPSY2010-64 RECONF2010-78 pp.169-174 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 15:10 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Real Chip evaluation of Silent Large Datapath:A Ultra Low Power Accelarater Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-110 CPSY2010-65 RECONF2010-79 |
Battery driven multi-media applications require both high performance and energy efficiency. Recon-figurable... [more] | VLD2010-110 CPSY2010-65 RECONF2010-79 pp.175-180 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 15:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Consideration of Window Join Operator over Data Streams by using FPGA Yuta Terada, Takefumi Miyoshi (UEC), Hideyuki Kawashima (Univ. Tsukuba), Tsutomu Yoshinaga (UEC) VLD2010-111 CPSY2010-66 RECONF2010-80 |
An implementation technique of window join operator by using FPGA is studied in order to improve the performance. Window... [more] | VLD2010-111 CPSY2010-66 RECONF2010-80 pp.181-186 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 16:05 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Validation of FPGA-based Many-core Simulator ScalableCore System Shinya Takamaeda, Ryosuke Sasakawa, Kenji Kise (Tokyo Tech) VLD2010-112 CPSY2010-67 RECONF2010-81 |
We have proposed and been developing the ScalableCore system, FPGA-based simulation system for tile many-core architectu... [more] | VLD2010-112 CPSY2010-67 RECONF2010-81 pp.187-192 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 16:25 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Implementation and Evaluation of a Fast and Handy LCD Module Using an FPGA Naoki Fujieda, Kenji Kise (Tokyo Tech) VLD2010-113 CPSY2010-68 RECONF2010-82 |
To output results of, or to debug, embedded systems, display modules which is easy to connect and shows much information... [more] | VLD2010-113 CPSY2010-68 RECONF2010-82 pp.193-198 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 16:45 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Gateway and Remote Call Mechanisms for a PC-FPGA Hybrid Cluster Masaki Kohata, Akira Uejima, Ryo Ozaki (Okayama Univ. of Sci.) VLD2010-114 CPSY2010-69 RECONF2010-83 |
Parallel processing by PC cluster and hardware acceleration by FPGA are useful technologies in a field of high performan... [more] | VLD2010-114 CPSY2010-69 RECONF2010-83 pp.199-204 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 17:05 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Design of Dataflow Machine on Multiple FPGAs Kenta Inakagata, Hirokazu Morishita (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) VLD2010-115 CPSY2010-70 RECONF2010-84 |
Recently, computational science has been utilized in various eld such as physics, chemistry and economics. Since the co... [more] | VLD2010-115 CPSY2010-70 RECONF2010-84 pp.205-210 |
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