| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-17
13:15 |
Tokyo |
Keio Univ. Hiyoshi Campus |
Achieve a preprocessing part of auditory sense with circuit
Yuya Usami, Hidehiko Arai, Etu Sou, Kazushi Takahashi, Toshitaka Nagano, Masatoshi Sekine (TUAT) |
[more] |
VLD2006-85 CPSY2006-56 RECONF2006-56
pp.1-6 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-17
13:40 |
Tokyo |
Keio Univ. Hiyoshi Campus |
FGPA Implementation of the Computing System RAPLAS for Ray-Tracing
Daichi Zaitsu, Yoshiyuki Kaeriyama, Kenichi Suzuki, Ryusuke Egawa (Tohoku Univ.), Nobuyuki Ohba (IBM Japan, Ltd.), Tadao Nakamura (Tohoku Univ.) |
[more] |
VLD2006-86 CPSY2006-57 RECONF2006-57
pp.7-12 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-17
14:05 |
Tokyo |
Keio Univ. Hiyoshi Campus |
Face detection with the union of hardware and software
Masatoshi Yokokawa, Ichiro Sudo, Tomomi Yuno, Masatoshi Sekine (TUAT) |
We build a face detection system with the coarse to fine algorithm. Coarse to Fine is the algorithm which uses the coars... [more] |
VLD2006-87 CPSY2006-58 RECONF2006-58
pp.13-18 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-17
14:50 |
Tokyo |
Keio Univ. Hiyoshi Campus |
Design of Residue Dividers Using Signed-Digit Number Residue Addition
Peng Jia, Shugang Wei (Gunma Univ.) |
(To be available after the conference date) [more] |
VLD2006-88 CPSY2006-59 RECONF2006-59
pp.19-24 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-17
15:15 |
Tokyo |
Keio Univ. Hiyoshi Campus |
GF(2^m) Digit-Serial Multiplier for Elliptic Curve Cryptosystem
Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Masao Yanagisawa, Satoshi Goto, Tatsuo Ohtsuki (Waseda Univ) |
[more] |
VLD2006-89 CPSY2006-60 RECONF2006-60
pp.25-30 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-17
16:00 |
Tokyo |
Keio Univ. Hiyoshi Campus |
A Parallel Algorithm Based on Genetic Algorithm and Tabu Search for LSI Floorplanning and Its Implementation on a PC Cluster
Takayoshi Shimazu, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.) |
This paper proposes a parallel floorplanning algorithm for VLSI floorplanning, which was based on genetic algorithm (GA)... [more] |
VLD2006-90 CPSY2006-61 RECONF2006-61
pp.31-36 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-17
16:25 |
Tokyo |
Keio Univ. Hiyoshi Campus |
A Hardware Algorithm for the Quadratic Assignment Problem Based on Tabu Search Using FPGAs
Yoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.) |
In this paper, a hardware algorithm for the quadratic assignment problem (QAP) based on tabu search was proposed. The p... [more] |
VLD2006-91 CPSY2006-62 RECONF2006-62
pp.37-42 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-17
16:50 |
Tokyo |
Keio Univ. Hiyoshi Campus |
Converting PLC instruction sequence into logic circuit: implementation and evaluation
Masanori Akinaka, Shuichi Ichikawa (Toyohashi Univ. Tech.) |
By implementing a control program with hard-wired logic using reconfigurable devices (e.g., FPGA), a flexible and highly... [more] |
VLD2006-92 CPSY2006-63 RECONF2006-63
pp.43-48 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-17
17:15 |
Tokyo |
Keio Univ. Hiyoshi Campus |
On efficient cut enumeration in technology mapping for FPGA
Yusuke Matsunaga (Kyushu Univ.) |
[more] |
VLD2006-93 CPSY2006-64 RECONF2006-64
pp.49-54 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-18
09:45 |
Tokyo |
Keio Univ. Hiyoshi Campus |
Optimum Code Scheduling for Clustered VLIW DSP Using Pseudo Boolean Satisfiability
Ryo Kobayashi, Yuuki Masui, Nagisa Ishiura (Kwansei Gakuin Univ.) |
[more] |
VLD2006-94 CPSY2006-65 RECONF2006-65
pp.1-5 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-18
10:10 |
Tokyo |
Keio Univ. Hiyoshi Campus |
Test Suite for C Compilers and Its Generating Tool testgen
Yuki Uchiyama (Kwansei Gakuin Univ.), Nobuyuki Hikichi (SRA), Nagisa Ishiura, Yuji Nagamatsu (Kwansei Gakuin Univ.) |
[more] |
VLD2006-95 CPSY2006-66 RECONF2006-66
pp.7-11 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-18
10:35 |
Tokyo |
Keio Univ. Hiyoshi Campus |
Development of C-Compiler for Educational Microprocessor COMET II
Ken Matsuda, Akira Sato, Kensuke Mori, Toshiyuki Tsutsumi (Meiji Univ.) |
[more] |
VLD2006-96 CPSY2006-67 RECONF2006-67
pp.13-18 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-18
11:00 |
Tokyo |
Keio Univ. Hiyoshi Campus |
CoDaMa: An XML-based Framework for Manipulating CDFGs
Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
This paper proposes an XML--based framework to manipulate CDFGs (Control Data Flow Graphs) for HW/SW (Hardware / Softwar... [more] |
VLD2006-97 CPSY2006-68 RECONF2006-68
pp.19-24 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-18
11:25 |
Tokyo |
Keio Univ. Hiyoshi Campus |
Model Checking of Cycle Accurate Hardware Behavior Models with Instantaneous Communication
Hirohisa Fujita, Masahiko Hamada, Tadaaki Tanimoto, Akio Nakata, Teruo Higashino (Osaka Univ.) |
Wiring delay imposes a limitation on
increase of clock frequency.
Therefore, instantaneous communications
consuming ... [more] |
VLD2006-98 CPSY2006-69 RECONF2006-69
pp.25-30 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-18
13:00 |
Tokyo |
Keio Univ. Hiyoshi Campus |
Construction Method for a Circuit by Multiplication
Satoshi Yano, Hayato Higuchi, Taichi Nagamoto, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
It shows that a connected graph which is composed of nodes which with max three links can be constructed to apply three ... [more] |
VLD2006-99 CPSY2006-70 RECONF2006-70
pp.31-35 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-18
13:25 |
Tokyo |
Keio Univ. Hiyoshi Campus |
Analysis of design architecture of ePLX ( embedded Programmable Logic matriX) and Evaluation of circuit mapping
Tomoo Hishida, Kouta Ishibashi, Shun Kimura, Naoki Okuno, Mitsutaka Matsumoto (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.) |
Recently, non-recurring engineering costs (NREs), including cost of mask-sets, and engineering design efforts are critic... [more] |
VLD2006-100 CPSY2006-71 RECONF2006-71
pp.37-42 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-18
13:50 |
Tokyo |
Keio Univ. Hiyoshi Campus |
Implementation of Dynamically Reconfigurable Processor MuCCRA
Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Hiroki Matsutani, Vasutan Tunbunheng, Adepu Parimala, Takashi Nishimura, Masaru Kato, Shotaro Saito, Toru Sano, Naomi Seki, Keiichiro Hirai, Mao KaiYi, Hideharu Amano (Keio Univ.) |
[more] |
VLD2006-101 CPSY2006-72 RECONF2006-72
pp.43-48 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-18
14:15 |
Tokyo |
Keio Univ. Hiyoshi Campus |
A Scheduling Algorithm for Multicast Configuration
Satoshi Tsutsumi, Vasutan Tunbunheng, Yohei Hasegawa, Hiroki Matsutani, Adepu Parimala, Takuro Nakamura, Takashi Nishimura, Toru Sano, Masaru Kato, Shotaro Saito, Naomi Seki, Keiichiro Hirai, Mao KaiYi, Hideharu Amano (Keio Univ.) |
[more] |
VLD2006-102 CPSY2006-73 RECONF2006-73
pp.49-54 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-18
14:55 |
Tokyo |
Keio Univ. Hiyoshi Campus |
Adoption and Evaluation of FPGA Partial Reconfiguration for a Run-time Reconfigurable System
Yukinobu Kiyota, Taiichiro Yatsunami, Takeru Kisanuki, Hideaki Yoshihiro, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
FPGA partial reconfiguration is the technique which make FPGA more flexible. We have studied about partial reconfigurati... [more] |
VLD2006-103 CPSY2006-74 RECONF2006-74
pp.55-60 |
| VLD, CPSY, RECONF, IPSJ-SLDM |
2007-01-18
15:20 |
Tokyo |
Keio Univ. Hiyoshi Campus |
Design and Implementation of Self Run-time Partial Reconfiguration System
Yohei Hori (AIST), Hiroyuki Yokoyama (KDDI Labs.), Hirofumi Sakane, Kenji Toda (AIST) |
We describe a design approach and its application of an FPGA-based system that utilizes self run-time partial reconfigur... [more] |
VLD2006-104 CPSY2006-75 RECONF2006-75
pp.61-68 |